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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
Andreas Hansson d8f732273e stats: Update stats for clean eviction addition
2015-07-30 03:42:27 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 2.825406 # Number of seconds simulated
sim_ticks 2825405893500 # Number of ticks simulated
final_tick 2825405893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 89977 # Simulator instruction rate (inst/s)
host_op_rate 109159 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 2115602490 # Simulator tick rate (ticks/s)
host_mem_usage 657340 # Number of bytes of host memory used
host_seconds 1335.51 # Real time elapsed on the host
sim_insts 120165205 # Number of instructions simulated
sim_ops 145782922 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 1275648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 1290856 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 182944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 606480 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 427776 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 12214872 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 1275648 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 182944 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1458592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8756928 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
system.physmem.bytes_written::total 8774492 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 22179 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 20690 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 131684 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2926 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 9496 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 6684 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 193712 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 136827 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
system.physmem.num_writes::total 141218 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 451492 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 456875 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 2982855 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 204 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 64750 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 214652 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 151403 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4323227 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 451492 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 64750 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 516242 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 3099352 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6202 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 3105569 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 3099352 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 451492 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 463077 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 2982855 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 204 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 64750 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 214667 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 151403 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7428796 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 193713 # Number of read requests accepted
system.physmem.writeReqs 141218 # Number of write requests accepted
system.physmem.readBursts 193713 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 141218 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 12387136 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 10496 # Total number of bytes read from write queue
system.physmem.bytesWritten 8786752 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 12214936 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8774492 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 164 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 49946 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 12421 # Per bank write bursts
system.physmem.perBankRdBursts::1 11965 # Per bank write bursts
system.physmem.perBankRdBursts::2 12291 # Per bank write bursts
system.physmem.perBankRdBursts::3 13088 # Per bank write bursts
system.physmem.perBankRdBursts::4 14558 # Per bank write bursts
system.physmem.perBankRdBursts::5 12211 # Per bank write bursts
system.physmem.perBankRdBursts::6 11940 # Per bank write bursts
system.physmem.perBankRdBursts::7 12041 # Per bank write bursts
system.physmem.perBankRdBursts::8 12092 # Per bank write bursts
system.physmem.perBankRdBursts::9 12171 # Per bank write bursts
system.physmem.perBankRdBursts::10 11769 # Per bank write bursts
system.physmem.perBankRdBursts::11 10768 # Per bank write bursts
system.physmem.perBankRdBursts::12 11340 # Per bank write bursts
system.physmem.perBankRdBursts::13 12292 # Per bank write bursts
system.physmem.perBankRdBursts::14 11321 # Per bank write bursts
system.physmem.perBankRdBursts::15 11281 # Per bank write bursts
system.physmem.perBankWrBursts::0 9078 # Per bank write bursts
system.physmem.perBankWrBursts::1 8838 # Per bank write bursts
system.physmem.perBankWrBursts::2 9120 # Per bank write bursts
system.physmem.perBankWrBursts::3 9597 # Per bank write bursts
system.physmem.perBankWrBursts::4 8379 # Per bank write bursts
system.physmem.perBankWrBursts::5 8806 # Per bank write bursts
system.physmem.perBankWrBursts::6 8536 # Per bank write bursts
system.physmem.perBankWrBursts::7 8489 # Per bank write bursts
system.physmem.perBankWrBursts::8 8658 # Per bank write bursts
system.physmem.perBankWrBursts::9 8679 # Per bank write bursts
system.physmem.perBankWrBursts::10 8573 # Per bank write bursts
system.physmem.perBankWrBursts::11 8021 # Per bank write bursts
system.physmem.perBankWrBursts::12 8348 # Per bank write bursts
system.physmem.perBankWrBursts::13 8584 # Per bank write bursts
system.physmem.perBankWrBursts::14 7909 # Per bank write bursts
system.physmem.perBankWrBursts::15 7678 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 13 # Number of times write queue was full causing retry
system.physmem.totGap 2825405630500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 550 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 3086 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 190049 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 136827 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 58643 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 71509 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 15316 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 12788 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 8414 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 7274 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 6278 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 5174 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 4590 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 1392 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 933 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 695 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 285 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 252 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2640 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 3080 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 4486 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 5017 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 5343 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 5977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6530 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 8098 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8572 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 9894 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 9480 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 9411 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8905 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 10669 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8786 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8210 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 7795 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 707 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 426 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 216 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 163 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 137 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 114 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 124 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 112 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 82 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 41 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 87370 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 242.346618 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 136.604135 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 304.406981 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 46631 53.37% 53.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 17108 19.58% 72.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5841 6.69% 79.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3374 3.86% 83.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2711 3.10% 86.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1534 1.76% 88.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 893 1.02% 89.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1014 1.16% 90.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 8264 9.46% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 87370 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6825 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.358242 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 561.081040 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047 6823 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6825 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6825 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 20.116190 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.646323 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 12.038338 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19 5646 82.73% 82.73% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23 406 5.95% 88.67% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 199 2.92% 91.59% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 55 0.81% 92.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 78 1.14% 93.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 151 2.21% 95.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 25 0.37% 96.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 11 0.16% 96.28% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 15 0.22% 96.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55 9 0.13% 96.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 8 0.12% 96.75% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 6 0.09% 96.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 163 2.39% 99.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 7 0.10% 99.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 2 0.03% 99.36% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 8 0.12% 99.47% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83 2 0.03% 99.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95 2 0.03% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 2 0.03% 99.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115 1 0.01% 99.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 2 0.03% 99.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 16 0.23% 99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.01% 99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151 1 0.01% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.01% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167 2 0.03% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6825 # Writes before turning the bus around for reads
system.physmem.totQLat 6500326386 # Total ticks spent queuing
system.physmem.totMemAccLat 10129370136 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 967745000 # Total ticks spent in databus transfers
system.physmem.avgQLat 33584.91 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 52334.91 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.38 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.11 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.32 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.47 # Average write queue length when enqueuing
system.physmem.readRowHits 161846 # Number of row buffer hits during reads
system.physmem.writeRowHits 81625 # Number of row buffer hits during writes
system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 59.44 # Row buffer hit rate for writes
system.physmem.avgGap 8435784.18 # Average gap between requests
system.physmem.pageHitRate 73.58 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 343821240 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 187600875 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 784017000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 459062640 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 79593993450 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 1625423449500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 1891333620465 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.402761 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 2703936458200 # Time in different power states
system.physmem_0.memoryStateTime::REF 94346460000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 27121665550 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 316695960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 172800375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 725657400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 430596000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184541675760 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 78590048175 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 1626304103250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 1891081576920 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.313555 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 2705408031049 # Time in different power states
system.physmem_1.memoryStateTime::REF 94346460000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 25651382451 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 192 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 320 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 24021626 # Number of BP lookups
system.cpu0.branchPred.condPredicted 15717395 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 977579 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 14633586 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 10784998 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 73.700308 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 3879887 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 32532 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.walks 65547 # Table walker walks requested
system.cpu0.dtb.walker.walksShort 65547 # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26411 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18806 # Level at which table walker walks with short descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 20330 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 45217 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 420.151713 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 2682.973536 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-8191 44150 97.64% 97.64% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::8192-16383 821 1.82% 99.46% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::16384-24575 92 0.20% 99.66% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::24576-32767 122 0.27% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::32768-40959 7 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::40960-49151 22 0.05% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 45217 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 15532 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 9209.084471 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 7773.401889 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 5863.053322 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-16383 14685 94.55% 94.55% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::16384-32767 794 5.11% 99.66% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::32768-49151 47 0.30% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 15532 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 89510783948 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.549501 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.505567 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 89461994948 99.95% 99.95% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 35577000 0.04% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 6153500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 3637000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 1264000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 750500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 798000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 605000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 4000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 89510783948 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 5141 79.20% 79.20% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M 1350 20.80% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 6491 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65547 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65547 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6491 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6491 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 72038 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 17771522 # DTB read hits
system.cpu0.dtb.read_misses 55962 # DTB read misses
system.cpu0.dtb.write_hits 14661221 # DTB write hits
system.cpu0.dtb.write_misses 9585 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3484 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 322 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 2338 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 800 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 17827484 # DTB read accesses
system.cpu0.dtb.write_accesses 14670806 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 32432743 # DTB hits
system.cpu0.dtb.misses 65547 # DTB misses
system.cpu0.dtb.accesses 32498290 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.walks 10460 # Table walker walks requested
system.cpu0.itb.walker.walksShort 10460 # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4240 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6125 # Level at which table walker walks with short descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 95 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 10365 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 435.745297 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 2168.024140 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-4095 9957 96.06% 96.06% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.42% 97.48% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::8192-12287 193 1.86% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::12288-16383 32 0.31% 99.65% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::16384-20479 11 0.11% 99.76% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::20480-24575 17 0.16% 99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::36864-40959 3 0.03% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 10365 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2678 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 10848.207618 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 9582.239797 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 5620.252827 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-8191 1037 38.72% 38.72% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::8192-16383 1516 56.61% 95.33% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::16384-24575 52 1.94% 97.27% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::24576-32767 65 2.43% 99.70% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.89% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2678 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 20779406712 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.976236 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.152563 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 494503000 2.38% 2.38% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 20284294712 97.62% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 517000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 92000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 20779406712 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 2260 87.50% 87.50% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M 323 12.50% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 2583 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10460 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10460 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2583 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2583 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 13043 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 37759439 # ITB inst hits
system.cpu0.itb.inst_misses 10460 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2357 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 1912 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 37769899 # ITB inst accesses
system.cpu0.itb.hits 37759439 # DTB hits
system.cpu0.itb.misses 10460 # DTB misses
system.cpu0.itb.accesses 37769899 # DTB accesses
system.cpu0.numCycles 130135672 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 18741348 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 112674064 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 24021626 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 14664885 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 105564363 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2824766 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 148935 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 59402 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 359448 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 427042 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 91226 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 37760092 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 271445 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 4846 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 126804147 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 1.071967 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.260919 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 64261882 50.68% 50.68% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 21462384 16.93% 67.60% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 8772204 6.92% 74.52% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 32307677 25.48% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 126804147 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.184589 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.865820 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 19721438 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 59617090 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 41434685 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 4962697 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1068237 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 3055964 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 348356 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 110795648 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 3978318 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 1068237 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 25470078 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 12211623 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 36823403 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 40512045 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 10718761 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 105720614 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 1057290 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 1452767 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 161700 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 58122 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 6514709 # Number of times rename has blocked due to SQ full
system.cpu0.rename.RenamedOperands 109806374 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 482725120 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 121004760 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9383 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 98259136 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 11547235 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 1229554 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 1088238 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 12335468 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 18754417 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 16214275 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 1701393 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 2256069 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 102765106 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 1695392 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 100794287 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 484302 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 9532947 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 22407435 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 122350 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 126804147 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.794882 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.031887 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 70515231 55.61% 55.61% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 23338464 18.41% 74.01% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 22507800 17.75% 91.76% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 9330414 7.36% 99.12% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 1112209 0.88% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 29 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 126804147 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 9354884 40.60% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 74 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.60% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 5601126 24.31% 64.90% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 8088042 35.10% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 66470143 65.95% 65.95% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 93430 0.09% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.04% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 8105 0.01% 66.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 18478690 18.33% 84.38% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 15741645 15.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 100794287 # Type of FU issued
system.cpu0.iq.rate 0.774532 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 23044126 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228625 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 351888789 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 114001116 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 98678663 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 32360 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9725 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 123815106 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 21034 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 363531 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 1999131 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 2544 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 19035 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 1014690 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 107294 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 362990 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1068237 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 1634305 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 175316 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 104635112 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 18754417 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 16214275 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 876681 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 26796 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 125236 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 19035 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 291770 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 399939 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 691709 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 99697701 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 18022679 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1031168 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 174614 # number of nop insts executed
system.cpu0.iew.exec_refs 33573838 # number of memory reference insts executed
system.cpu0.iew.exec_branches 16859604 # Number of branches executed
system.cpu0.iew.exec_stores 15551159 # Number of stores executed
system.cpu0.iew.exec_rate 0.766106 # Inst execution rate
system.cpu0.iew.wb_sent 99140543 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 98688388 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 51348142 # num instructions producing a value
system.cpu0.iew.wb_consumers 84871692 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.wb_rate 0.758350 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.605009 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitSquashedInsts 8492759 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1573042 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 633433 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 125053157 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.760074 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.473514 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 80626724 64.47% 64.47% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 24772258 19.81% 84.28% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 8266840 6.61% 90.89% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 3238221 2.59% 93.48% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 3432782 2.75% 96.23% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 1539199 1.23% 97.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 1134355 0.91% 98.37% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 546479 0.44% 98.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 1496299 1.20% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 125053157 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 78998098 # Number of instructions committed
system.cpu0.commit.committedOps 95049599 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 31954871 # Number of memory references committed
system.cpu0.commit.loads 16755286 # Number of loads committed
system.cpu0.commit.membars 647733 # Number of memory barriers committed
system.cpu0.commit.branches 16226575 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 81983360 # Number of committed integer instructions.
system.cpu0.commit.function_calls 1932291 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 62995577 66.28% 66.28% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 91046 0.10% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.37% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 8105 0.01% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 16755286 17.63% 84.01% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 15199585 15.99% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 95049599 # Class of committed instruction
system.cpu0.commit.bw_lim_events 1496299 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 222908078 # The number of ROB reads
system.cpu0.rob.rob_writes 208834787 # The number of ROB writes
system.cpu0.timesIdled 129596 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 3331525 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 5520676264 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 78876046 # Number of Instructions Simulated
system.cpu0.committedOps 94927547 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.649876 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.649876 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.606106 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.606106 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 110754452 # number of integer regfile reads
system.cpu0.int_regfile_writes 59798186 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8167 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
system.cpu0.cc_regfile_reads 351214590 # number of cc regfile reads
system.cpu0.cc_regfile_writes 41113323 # number of cc regfile writes
system.cpu0.misc_regfile_reads 177297499 # number of misc regfile reads
system.cpu0.misc_regfile_writes 1225193 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 713718 # number of replacements
system.cpu0.dcache.tags.tagsinuse 494.250179 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 28854841 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 714230 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 40.399929 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 274766500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.250179 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965332 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.965332 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 63563549 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 63563549 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 15604955 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 15604955 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 12027073 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 12027073 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310316 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 310316 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363058 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 363058 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361354 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 361354 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 27632028 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 27632028 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 27942344 # number of overall hits
system.cpu0.dcache.overall_hits::total 27942344 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 644494 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 644494 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 1893203 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 1893203 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147485 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 147485 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25333 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 25333 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20104 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 20104 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 2537697 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 2537697 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 2685182 # number of overall misses
system.cpu0.dcache.overall_misses::total 2685182 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8536879000 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 8536879000 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27482436369 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 27482436369 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389618000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 389618000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 450883500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 450883500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 454000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 454000 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 36019315369 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 36019315369 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 36019315369 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 36019315369 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 16249449 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 16249449 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 13920276 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 13920276 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457801 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 457801 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388391 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 388391 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381458 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381458 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 30169725 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 30169725 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 30627526 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 30627526 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039663 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.039663 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136003 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.136003 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.322160 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.322160 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065226 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065226 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052703 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052703 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084114 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.084114 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087672 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.087672 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13245.862646 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 13245.862646 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14516.370600 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 14516.370600 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15379.860261 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15379.860261 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22427.551731 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22427.551731 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14193.702152 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 14193.702152 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13414.105773 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 13414.105773 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 682 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 4150493 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 202595 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 20.486651 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 517170 # number of writebacks
system.cpu0.dcache.writebacks::total 517170 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 254611 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 254611 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1567828 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 1567828 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18755 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18755 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822439 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 1822439 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822439 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 1822439 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 389883 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 389883 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325375 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 325375 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102048 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 102048 # number of SoftPFReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6578 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6578 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20104 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 20104 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 715258 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 715258 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 817306 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 817306 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39472 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4555035000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4555035000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5512912898 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5512912898 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1660765500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1660765500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 101006000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 101006000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 430792500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 430792500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 441000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 441000 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10067947898 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 10067947898 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11728713398 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 11728713398 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4315293000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4315293000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3299266500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3299266500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7614559500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7614559500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023994 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023994 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023374 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023374 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222909 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222909 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016937 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016937 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052703 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052703 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023708 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.023708 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026685 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.026685 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11683.081848 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11683.081848 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16943.259003 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16943.259003 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16274.356185 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16274.356185 # average SoftPFReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15355.123138 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15355.123138 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21428.198368 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21428.198368 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14075.966851 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14075.966851 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14350.455518 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14350.455518 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 211679.240655 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 211679.240655 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 172863.171959 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172863.171959 # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 192910.404844 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 192910.404844 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1264231 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.765651 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 36438607 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 1264743 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 28.811076 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 6439669000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.765651 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999542 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999542 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 76777836 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 76777836 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 36438607 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 36438607 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 36438607 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 36438607 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 36438607 # number of overall hits
system.cpu0.icache.overall_hits::total 36438607 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 1317920 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 1317920 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 1317920 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 1317920 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 1317920 # number of overall misses
system.cpu0.icache.overall_misses::total 1317920 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13045197783 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 13045197783 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 13045197783 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 13045197783 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 13045197783 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 13045197783 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 37756527 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 37756527 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 37756527 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 37756527 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 37756527 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 37756527 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034906 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.034906 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034906 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.034906 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034906 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.034906 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9898.322951 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9898.322951 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9898.322951 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9898.322951 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9898.322951 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1585730 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 630 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 117915 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.448077 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 57.272727 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53136 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 53136 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 53136 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 53136 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 53136 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 53136 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264784 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 1264784 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 1264784 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 1264784 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 1264784 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1264784 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11837775153 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11837775153 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11837775153 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 11837775153 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11837775153 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 11837775153 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033498 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.033498 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033498 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.033498 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9359.523170 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9359.523170 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 9359.523170 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.l2cache.prefetcher.num_hwpf_issued 1848695 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 1851312 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 2366 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 233112 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements 279786 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 16110.932478 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 3625969 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 296031 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 12.248612 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2809841331000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 7402.389300 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.896732 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.359713 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5003.167978 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1996.783797 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1695.334959 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.451806 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000726 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000083 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.305369 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121874 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.103475 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.983333 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1041 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15195 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 33 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 317 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 403 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 288 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 425 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4805 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7004 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2900 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.063538 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927429 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 66593364 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 66593364 # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 52693 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12386 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 65079 # number of ReadReq hits
system.cpu0.l2cache.Writeback_hits::writebacks 517165 # number of Writeback hits
system.cpu0.l2cache.Writeback_hits::total 517165 # number of Writeback hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28793 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 28793 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1744 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 1744 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223098 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 223098 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1208893 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 1208893 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 400319 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 400319 # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 52693 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12386 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 1208893 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 623417 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 1897389 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 52693 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12386 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 1208893 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 623417 # number of overall hits
system.cpu0.l2cache.overall_hits::total 1897389 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 398 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 555 # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26381 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 26381 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18360 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 18360 # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47293 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 47293 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55856 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 55856 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98075 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 98075 # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 398 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 157 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 55856 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 145368 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 201779 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 398 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 157 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst 55856 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data 145368 # number of overall misses
system.cpu0.l2cache.overall_misses::total 201779 # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10822500 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3611000 # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total 14433500 # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 484495000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total 484495000 # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 371083000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 371083000 # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 421500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 421500 # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2673446497 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total 2673446497 # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2697437499 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2697437499 # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2928360998 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2928360998 # number of ReadSharedReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10822500 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3611000 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2697437499 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data 5601807495 # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total 8313678494 # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10822500 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3611000 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2697437499 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data 5601807495 # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total 8313678494 # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 53091 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12543 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total 65634 # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::writebacks 517165 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.Writeback_accesses::total 517165 # number of Writeback accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55174 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total 55174 # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20104 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total 20104 # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270391 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total 270391 # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1264749 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total 1264749 # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 498394 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total 498394 # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 53091 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12543 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst 1264749 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data 768785 # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total 2099168 # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 53091 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12543 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst 1264749 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data 768785 # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total 2099168 # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012517 # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total 0.008456 # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478142 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478142 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.913251 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.913251 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.174906 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total 0.174906 # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.044164 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.044164 # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.196782 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.196782 # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012517 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.044164 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.189088 # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total 0.096123 # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007497 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012517 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.044164 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.189088 # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total 0.096123 # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23000 # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26006.306306 # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18365.300785 # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18365.300785 # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20211.492375 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20211.492375 # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56529.433468 # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56529.433468 # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 48292.708017 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 48292.708017 # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 29858.383869 # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 29858.383869 # average ReadSharedReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 41201.901556 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27192.211055 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23000 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 48292.708017 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38535.355064 # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 41201.901556 # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs 214 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 26.750000 # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
system.cpu0.l2cache.writebacks::writebacks 197696 # number of writebacks
system.cpu0.l2cache.writebacks::total 197696 # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5476 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total 5476 # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 32 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 32 # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 797 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 797 # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6273 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total 6306 # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6273 # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total 6306 # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 398 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 156 # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total 554 # number of ReadReq MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8991 # number of CleanEvict MSHR misses
system.cpu0.l2cache.CleanEvict_mshr_misses::total 8991 # number of CleanEvict MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total 245693 # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26381 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26381 # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18360 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18360 # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41817 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total 41817 # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 55824 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 55824 # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97278 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97278 # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 398 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 156 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 55824 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data 139095 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total 195473 # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 398 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 156 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 55824 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data 139095 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 245693 # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total 441166 # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 23390 # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 19086 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 19086 # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 39472 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 42476 # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2662500 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11097000 # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15042795977 # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 537912499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 537912499 # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 278663498 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 278663498 # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 343500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 343500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1730970000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1730970000 # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2361388499 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2361388499 # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2303131998 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2303131998 # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2662500 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2361388499 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4034101998 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total 6406587497 # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8434500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2662500 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2361388499 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4034101998 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15042795977 # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 21449383474 # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243342000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4152104000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4395446000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3153204958 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3153204958 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243342000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7305308958 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7548650958 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008441 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478142 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478142 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.913251 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.913251 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.154654 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.154654 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.044138 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.195183 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.195183 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093119 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007497 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012437 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.044138 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180928 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210162 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20030.685921 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61225.985181 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20390.148175 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20390.148175 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15177.750436 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15177.750436 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41393.930698 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41393.930698 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42300.596500 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 23675.774564 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 23675.774564 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32774.794969 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21192.211055 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17067.307692 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42300.596500 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29002.494683 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61225.985181 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48619.756450 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 203674.286275 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 187919.880291 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165210.361417 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 165210.361417 # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 185075.723500 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 177715.673745 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 118491 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1915950 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 30902 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 19086 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::Writeback 881917 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1558941 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 295049 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 88486 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42808 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 113105 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 298585 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 285519 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1264784 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 601994 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3774932 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2575467 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29033 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 117114 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 6496546 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80991872 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86506920 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50172 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 212364 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 167761328 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 1157195 # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples 5250259 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 1.213502 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.409779 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 4129320 78.65% 78.65% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 1120939 21.35% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 5250259 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 2631653442 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 114940499 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 1900515323 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 1221760496 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 16493992 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 64044457 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 33870827 # Number of BP lookups
system.cpu1.branchPred.condPredicted 11547618 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 303923 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 18735544 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 14949091 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 79.790002 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 12480037 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 7268 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.walks 21101 # Table walker walks requested
system.cpu1.dtb.walker.walksShort 21101 # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8660 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5796 # Level at which table walker walks with short descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 6645 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 14456 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 508.058937 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 2886.331667 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-4095 13910 96.22% 96.22% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::4096-8191 137 0.95% 97.17% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::8192-12287 242 1.67% 98.84% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::12288-16383 68 0.47% 99.32% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.14% 99.45% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::20480-24575 12 0.08% 99.54% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::24576-28671 37 0.26% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::28672-32767 11 0.08% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-36863 15 0.10% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 14456 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 5194 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 9424.913362 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 8003.762670 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 6175.333367 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-8191 2569 49.46% 49.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2132 41.05% 90.51% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::16384-24575 361 6.95% 97.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::24576-32767 99 1.91% 99.36% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.06% 99.42% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::40960-49151 27 0.52% 99.94% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 5194 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 72058045764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.162272 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.372420 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0 60402096044 83.82% 83.82% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::1 11637981720 16.15% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2 11426500 0.02% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::3 2950500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4 950000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::5 753000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6 773000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::7 312500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8 161500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::9 148500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10 75000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12 134500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::13 51500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14 27000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::15 156500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 72058045764 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 1910 75.91% 75.91% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M 606 24.09% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 2516 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21101 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21101 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2516 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2516 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 23617 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 10151644 # DTB read hits
system.cpu1.dtb.read_misses 18305 # DTB read misses
system.cpu1.dtb.write_hits 6523716 # DTB write hits
system.cpu1.dtb.write_misses 2796 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 50 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 456 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 384 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 10169949 # DTB read accesses
system.cpu1.dtb.write_accesses 6526512 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 16675360 # DTB hits
system.cpu1.dtb.misses 21101 # DTB misses
system.cpu1.dtb.accesses 16696461 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.walks 6899 # Table walker walks requested
system.cpu1.itb.walker.walksShort 6899 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4113 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2729 # Level at which table walker walks with short descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 57 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 6842 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 198.333821 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 1594.183488 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-4095 6730 98.36% 98.36% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.86% 99.23% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::8192-12287 21 0.31% 99.53% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::12288-16383 14 0.20% 99.74% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.10% 99.84% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.07% 99.91% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 6842 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1221 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 10738.329238 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 9530.760976 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 5854.425690 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-4095 35 2.87% 2.87% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::4096-8191 374 30.63% 33.50% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 40.70% 74.20% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::12288-16383 243 19.90% 94.10% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::16384-20479 3 0.25% 94.35% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::20480-24575 9 0.74% 95.09% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::24576-28671 37 3.03% 98.12% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.31% 99.43% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::36864-40959 2 0.16% 99.59% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.25% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::53248-57343 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1221 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 11897679120 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.980675 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.137806 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 230157764 1.93% 1.93% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 11667291856 98.06% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 229500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 11897679120 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 997 85.65% 85.65% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 167 14.35% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1164 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6899 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1164 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1164 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 8063 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 43584522 # ITB inst hits
system.cpu1.itb.inst_misses 6899 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 1193 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 547 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 43591421 # ITB inst accesses
system.cpu1.itb.hits 43584522 # DTB hits
system.cpu1.itb.misses 6899 # DTB misses
system.cpu1.itb.accesses 43591421 # DTB accesses
system.cpu1.numCycles 105332010 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 10132151 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 108981973 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 33870827 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 27429128 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 92017725 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3770452 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 88186 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 36483 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 195284 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 298638 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 22598 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 43583923 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 117443 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 2417 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 104676291 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.289820 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.339564 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 47827120 45.69% 45.69% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 14002469 13.38% 59.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 7529046 7.19% 66.26% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 35317656 33.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 104676291 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.321563 # Number of branch fetches per cycle
system.cpu1.fetch.rate 1.034652 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 13137871 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 61997568 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 26684640 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1104927 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1751285 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 750757 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 136902 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 67935331 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 1160131 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 1751285 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 17557644 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 2234457 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 57207184 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 23346153 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 2579568 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 55040039 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 231549 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 250107 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 36576 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 14638 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 1569614 # Number of times rename has blocked due to SQ full
system.cpu1.rename.RenamedOperands 54888875 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 259969011 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 58535420 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1673 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 52136282 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 2752593 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 1876398 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1803595 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 13068910 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 10432997 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 6892596 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 625658 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 847753 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 54148527 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 587967 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 53807238 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 110933 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 3881118 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 5762517 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 48708 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 104676291 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.514035 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 0.850765 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 71469096 68.28% 68.28% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 16529250 15.79% 84.07% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 13041841 12.46% 96.53% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 3350126 3.20% 99.73% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 285962 0.27% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 16 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 104676291 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 2912792 45.01% 45.01% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 674 0.01% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.02% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 1671813 25.83% 70.85% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 1886405 29.15% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 36660342 68.13% 68.13% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 45736 0.08% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3323 0.01% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 10366546 19.27% 87.49% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 6731225 12.51% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 53807238 # Type of FU issued
system.cpu1.iq.rate 0.510835 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 6471684 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.120275 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 218867204 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 58625584 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 51813824 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 6180 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2068 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 60274803 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 4053 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 90118 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 483730 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 680 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 10069 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 351136 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 51537 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 78201 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1751285 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 538520 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 104583 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 54788620 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 10432997 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 6892596 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 301008 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 9394 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 87795 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 10069 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 55171 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 126265 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 181436 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 53538867 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 10265396 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 247288 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 52126 # number of nop insts executed
system.cpu1.iew.exec_refs 16932944 # number of memory reference insts executed
system.cpu1.iew.exec_branches 11793778 # Number of branches executed
system.cpu1.iew.exec_stores 6667548 # Number of stores executed
system.cpu1.iew.exec_rate 0.508287 # Inst execution rate
system.cpu1.iew.wb_sent 53390597 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 51815609 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 25160275 # num instructions producing a value
system.cpu1.iew.wb_consumers 38370093 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.wb_rate 0.491927 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.655726 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitSquashedInsts 3631838 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 539259 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 169982 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 102749355 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.495266 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.156980 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 77230128 75.16% 75.16% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 14246960 13.87% 89.03% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6071957 5.91% 94.94% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 703815 0.68% 95.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 1976351 1.92% 97.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 1539288 1.50% 99.05% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 468880 0.46% 99.50% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 125021 0.12% 99.62% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 386955 0.38% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 102749355 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 41322014 # Number of instructions committed
system.cpu1.commit.committedOps 50888230 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 16490727 # Number of memory references committed
system.cpu1.commit.loads 9949267 # Number of loads committed
system.cpu1.commit.membars 209363 # Number of memory barriers committed
system.cpu1.commit.branches 11627773 # Number of branches committed
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 45743033 # Number of committed integer instructions.
system.cpu1.commit.function_calls 3362907 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 34349326 67.50% 67.50% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 44854 0.09% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 3323 0.01% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 9949267 19.55% 87.15% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 6541460 12.85% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 50888230 # Class of committed instruction
system.cpu1.commit.bw_lim_events 386955 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 136861200 # The number of ROB reads
system.cpu1.rob.rob_writes 110963404 # The number of ROB writes
system.cpu1.timesIdled 59136 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 655719 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5544933026 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 41289159 # Number of Instructions Simulated
system.cpu1.committedOps 50855375 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 2.551082 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 2.551082 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.391991 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.391991 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 56164709 # number of integer regfile reads
system.cpu1.int_regfile_writes 35664798 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1398 # number of floating regfile reads
system.cpu1.fp_regfile_writes 516 # number of floating regfile writes
system.cpu1.cc_regfile_reads 190801964 # number of cc regfile reads
system.cpu1.cc_regfile_writes 15538939 # number of cc regfile writes
system.cpu1.misc_regfile_reads 145958777 # number of misc regfile reads
system.cpu1.misc_regfile_writes 388038 # number of misc regfile writes
system.cpu1.dcache.tags.replacements 188683 # number of replacements
system.cpu1.dcache.tags.tagsinuse 469.137779 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 15712566 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 189037 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 83.118998 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 93446032500 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.137779 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.916285 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.916285 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 32914145 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 32914145 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 9558582 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 9558582 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 5897409 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 5897409 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49196 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 49196 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78850 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 78850 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70461 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 70461 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 15455991 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 15455991 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 15505187 # number of overall hits
system.cpu1.dcache.overall_hits::total 15505187 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 218229 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 218229 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 396239 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 396239 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 29850 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 29850 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18125 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 18125 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23674 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 23674 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 614468 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 614468 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 644318 # number of overall misses
system.cpu1.dcache.overall_misses::total 644318 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3487669000 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 3487669000 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9663134455 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 9663134455 # number of WriteReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 358154500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 358154500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 554726500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 554726500 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 887500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 887500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 13150803455 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 13150803455 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 13150803455 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 13150803455 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 9776811 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 9776811 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 6293648 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 6293648 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79046 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 79046 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96975 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 96975 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94135 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 94135 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 16070459 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 16070459 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 16149505 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 16149505 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022321 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.022321 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062959 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.062959 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377628 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377628 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186904 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186904 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.251490 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.251490 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038236 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.038236 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039897 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.039897 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15981.693542 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15981.693542 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24387.136185 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 24387.136185 # average WriteReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19760.248276 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19760.248276 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23431.887303 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23431.887303 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21401.933795 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 21401.933795 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20410.423820 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 20410.423820 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 334 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 1417697 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 34 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 39735 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.823529 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 35.678797 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
system.cpu1.dcache.writebacks::writebacks 116769 # number of writebacks
system.cpu1.dcache.writebacks::total 116769 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 80049 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 80049 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306072 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 306072 # number of WriteReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13108 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13108 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 386121 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 386121 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 386121 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 386121 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 138180 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 138180 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90167 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 90167 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28614 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 28614 # number of SoftPFReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5017 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5017 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23674 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 23674 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 228347 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 228347 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 256961 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 256961 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14486 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26301 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1915104500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1915104500 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2355138466 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2355138466 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 482351500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 482351500 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 90011000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 90011000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 531068500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 531068500 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 871500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 871500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4270242966 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 4270242966 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4752594466 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 4752594466 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2349248500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2349248500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1864740000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1864740000 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4213988500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4213988500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014133 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014133 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014327 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014327 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.361992 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.361992 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051735 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051735 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.251490 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.251490 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014209 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015911 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.015911 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13859.491243 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13859.491243 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26119.738552 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26119.738552 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16857.185294 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16857.185294 # average SoftPFReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17941.199920 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17941.199920 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22432.563149 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22432.563149 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18700.674701 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18700.674701 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18495.392165 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18495.392165 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 162173.719453 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162173.719453 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157828.184511 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 157828.184511 # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 160221.607543 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 160221.607543 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 603214 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.475238 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 42957427 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 603726 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 71.153846 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 78885354000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.475238 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975538 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975538 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 87771063 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 87771063 # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst 42957427 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 42957427 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 42957427 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 42957427 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 42957427 # number of overall hits
system.cpu1.icache.overall_hits::total 42957427 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 626240 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 626240 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 626240 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 626240 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 626240 # number of overall misses
system.cpu1.icache.overall_misses::total 626240 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5487739407 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 5487739407 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 5487739407 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 5487739407 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 5487739407 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 5487739407 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 43583667 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 43583667 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 43583667 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 43583667 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 43583667 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 43583667 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014369 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.014369 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014369 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.014369 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014369 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.014369 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8762.997265 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 8762.997265 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 8762.997265 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8762.997265 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 8762.997265 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 503899 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 26 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 46132 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.922982 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 26 # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22511 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 22511 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 22511 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 22511 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 22511 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 22511 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 603729 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 603729 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 603729 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 603729 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 603729 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 603729 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5031797233 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 5031797233 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5031797233 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 5031797233 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5031797233 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 5031797233 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9110000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9110000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9110000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 9110000 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013852 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.013852 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013852 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.013852 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8334.529620 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8334.529620 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 8334.529620 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 89313.725490 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 89313.725490 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 89313.725490 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.l2cache.prefetcher.num_hwpf_issued 189065 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 189671 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 541 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 56769 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements 48663 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 15171.630527 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 1474911 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 63236 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 23.323914 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 8232.224686 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 11.332834 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.684874 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3831.793838 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2451.411988 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 641.182307 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.502455 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000692 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000225 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.233874 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.149622 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.039135 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.926003 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1118 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 35 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13420 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 930 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 167 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 10 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8633 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4319 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068237 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002136 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.819092 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 27275895 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 27275895 # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 15350 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7200 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 22550 # number of ReadReq hits
system.cpu1.l2cache.Writeback_hits::writebacks 116768 # number of Writeback hits
system.cpu1.l2cache.Writeback_hits::total 116768 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1559 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 1559 # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 954 # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total 954 # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27353 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 27353 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 586865 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 586865 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101704 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 101704 # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 15350 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7200 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 586865 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 129057 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 738472 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 15350 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7200 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 586865 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 129057 # number of overall hits
system.cpu1.l2cache.overall_hits::total 738472 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 400 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 278 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 678 # number of ReadReq misses
system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses
system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28175 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 28175 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22720 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 22720 # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33751 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 33751 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16862 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 16862 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 70088 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 70088 # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 400 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 278 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 16862 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 103839 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 121379 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 400 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 278 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 16862 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 103839 # number of overall misses
system.cpu1.l2cache.overall_misses::total 121379 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8778500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5791500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 14570000 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536726500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 536726500 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 459045500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 459045500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 847500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 847500 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1378926000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 1378926000 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 607258000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 607258000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1556092998 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1556092998 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8778500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5791500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 607258000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 2935018998 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 3556846998 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8778500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5791500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 607258000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 2935018998 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 3556846998 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 15750 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7478 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 23228 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::writebacks 116769 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.Writeback_accesses::total 116769 # number of Writeback accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29734 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 29734 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23674 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 23674 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61104 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 61104 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 603727 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 603727 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 171792 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 171792 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 15750 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7478 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 603727 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 232896 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 859851 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 15750 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7478 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 603727 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 232896 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 859851 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037176 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.029189 # miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000009 # miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_miss_rate::total 0.000009 # miss rate for Writeback accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.947568 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.947568 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.959703 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.959703 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.552353 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.552353 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.027930 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.027930 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.407982 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.407982 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037176 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.027930 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.445860 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.141163 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025397 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037176 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.027930 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.445860 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.141163 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20832.733813 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21489.675516 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19049.742680 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19049.742680 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20204.467430 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20204.467430 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40855.856123 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40855.856123 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36013.402918 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36013.402918 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22201.988900 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22201.988900 # average ReadSharedReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 29303.643942 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21946.250000 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20832.733813 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36013.402918 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28265.093058 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 29303.643942 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 22.800000 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
system.cpu1.l2cache.writebacks::writebacks 30215 # number of writebacks
system.cpu1.l2cache.writebacks::total 30215 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 14 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 420 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 420 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 76 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 76 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 14 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 496 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 516 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 14 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 496 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 516 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 400 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 264 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 664 # number of ReadReq MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses
system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 2169 # number of CleanEvict MSHR misses
system.cpu1.l2cache.CleanEvict_mshr_misses::total 2169 # number of CleanEvict MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 23681 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28175 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28175 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22720 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22720 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33331 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 33331 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 16856 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 16856 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 70012 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 70012 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 400 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 264 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 16856 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 103343 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 120863 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 400 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 264 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 16856 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 103343 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 23681 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 144544 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 14486 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 14588 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 11815 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 11815 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26301 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26403 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4031500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10410000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1037990412 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 463119500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 463119500 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 352921500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 352921500 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 751500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 751500 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1120597500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1120597500 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 506014500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 506014500 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1134157998 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1134157998 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4031500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 506014500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2254755498 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 2771179998 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6378500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4031500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 506014500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2254755498 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1037990412 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 3809170410 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8345000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2233165500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2241510500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1776007998 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1776007998 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8345000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 4009173498 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 4017518498 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028586 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000009 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000009 # mshr miss rate for Writeback accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.947568 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.947568 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.959703 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.959703 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.545480 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.545480 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027920 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.407539 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.407539 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140563 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025397 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035304 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027920 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443730 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.168104 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15677.710843 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43832.203539 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16437.249335 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16437.249335 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15533.516725 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15533.516725 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33620.278419 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33620.278419 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30019.844566 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16199.480061 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16199.480061 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22928.274145 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15946.250000 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15270.833333 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30019.844566 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.173442 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43832.203539 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26353.016452 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 154160.258180 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 153654.407732 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150318.070080 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150318.070080 # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 81813.725490 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 152434.260979 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 152161.439912 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 67801 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 858839 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 11815 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::Writeback 481520 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 790490 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 28803 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 75635 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42021 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 86708 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 83417 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 65666 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 603729 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 520017 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1799792 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 888351 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17049 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 36002 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 2741194 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38640160 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25264094 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29912 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 63000 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 63997166 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 1119232 # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples 2773999 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 1.384160 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.486396 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 1708339 61.58% 61.58% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 1065660 38.42% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 2773999 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 991762490 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 81878499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 905763364 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 398007900 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 9580481 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 20262978 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
system.iobus.trans_dist::WriteReq 59421 # Transaction distribution
system.iobus.trans_dist::WriteResp 59421 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 107914 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36458 # number of replacements
system.iocache.tags.tagsinuse 14.557293 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 254755320000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide 14.557293 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.909831 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.909831 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 328284 # Number of tag accesses
system.iocache.tags.data_accesses 328284 # Number of data accesses
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 252 # number of overall misses
system.iocache.overall_misses::total 252 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 32401877 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 32401877 # number of ReadReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 4274240561 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 4274240561 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 32401877 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 32401877 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 32401877 # number of overall miss cycles
system.iocache.overall_miss_latency::total 32401877 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 128578.876984 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 128578.876984 # average ReadReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117994.715134 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 117994.715134 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 128578.876984 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 128578.876984 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 128578.876984 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 36206 # number of writebacks
system.iocache.writebacks::total 36206 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 19801877 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 19801877 # number of ReadReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463040561 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 2463040561 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 19801877 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 19801877 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 19801877 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 19801877 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78578.876984 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 78578.876984 # average ReadReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67994.715134 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67994.715134 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 78578.876984 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 78578.876984 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 130408 # number of replacements
system.l2c.tags.tagsinuse 64065.129893 # Cycle average of tags in use
system.l2c.tags.total_refs 410009 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 194847 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 2.104261 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 11642.697009 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.974901 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.090106 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 8094.672337 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 2978.207969 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37076.471677 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.445472 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909924 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 1874.720720 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 683.354796 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1693.584982 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.177653 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000213 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.123515 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.045444 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.565742 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.028606 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.010427 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.025842 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.977556 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 31097 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 33320 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 200 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 5745 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 25152 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 22 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 514 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6128 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 26654 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.474503 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.000336 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.508423 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 5488101 # Number of tag accesses
system.l2c.tags.data_accesses 5488101 # Number of data accesses
system.l2c.Writeback_hits::writebacks 227912 # number of Writeback hits
system.l2c.Writeback_hits::total 227912 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2549 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 581 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 3130 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 167 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 333 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 3885 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 1531 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 5416 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 182 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 36625 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 47695 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 45738 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 45 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 34 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 14003 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 9344 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 4694 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 158438 # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker 182 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 36625 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 51580 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 45738 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 45 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 14003 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 10875 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 4694 # number of demand (read+write) hits
system.l2c.demand_hits::total 163854 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 182 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits
system.l2c.overall_hits::cpu0.inst 36625 # number of overall hits
system.l2c.overall_hits::cpu0.data 51580 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 45738 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 45 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits
system.l2c.overall_hits::cpu1.inst 14003 # number of overall hits
system.l2c.overall_hits::cpu1.data 10875 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 4694 # number of overall hits
system.l2c.overall_hits::total 163854 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 8869 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 2831 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 11700 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 686 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 1243 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1929 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 11279 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 8332 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 19611 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 19189 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 9101 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 131841 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 9 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 2845 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 1165 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 6684 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 170863 # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 19189 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 20380 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 131841 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 9 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 2845 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 9497 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 6684 # number of demand (read+write) misses
system.l2c.demand_misses::total 190474 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses
system.l2c.overall_misses::cpu0.inst 19189 # number of overall misses
system.l2c.overall_misses::cpu0.data 20380 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 131841 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 9 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 2845 # number of overall misses
system.l2c.overall_misses::cpu1.data 9497 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 6684 # number of overall misses
system.l2c.overall_misses::total 190474 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 8584000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 2028000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 10612000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1081500 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1017000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 2098500 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 1148001500 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 689593000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 1837594500 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2446500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 248000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1585577501 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 820774000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 820000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 310000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 240581000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 107330500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 17931347537 # number of ReadSharedReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 2446500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 248000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 1585577501 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 1968775500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 820000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 310000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 240581000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 796923500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 19768942037 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 2446500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 248000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 1585577501 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 1968775500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14236289443 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 820000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 310000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 240581000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 796923500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 936970593 # number of overall miss cycles
system.l2c.overall_miss_latency::total 19768942037 # number of overall miss cycles
system.l2c.Writeback_accesses::writebacks 227912 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 227912 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 11418 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 3412 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 14830 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 853 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 1409 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2262 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 15164 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 9863 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 25027 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 207 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 81 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 55814 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 56796 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 177579 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 54 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 16848 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 10509 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 11378 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 329301 # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 207 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 81 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 55814 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 71960 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177579 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 54 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 16848 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 20372 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11378 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 354328 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 207 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 81 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 55814 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 71960 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177579 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 54 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 16848 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 20372 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11378 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 354328 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.776756 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829719 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.788941 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.804220 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.882186 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.852785 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.743801 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.844773 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.783594 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.037037 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.343803 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.160240 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.168863 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.110857 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.518866 # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.037037 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.343803 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.283213 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.168863 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.466179 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.537564 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.120773 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.037037 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.343803 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.283213 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.742436 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.166667 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.168863 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.466179 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.587449 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.537564 # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 967.865599 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 716.354645 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 907.008547 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1576.530612 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 818.181818 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 1087.869362 # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101782.205869 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82764.402304 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 93702.233440 # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 97860 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 82666.666667 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82629.501329 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 90185.034612 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 107980.745314 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 91111.111111 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 310000 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84562.741652 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 92129.184549 # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 140181.118043 # average ReadSharedReq miss latency
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for ReadSharedReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::total 0.518829 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.120773 # mshr miss rate for demand accesses
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system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.166667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for demand accesses
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system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.168329 # mshr miss rate for overall accesses
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system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.587449 # mshr miss rate for overall accesses
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system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average ReadSharedReq mshr miss latency
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system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average ReadSharedReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 87860 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72666.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72626.811269 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86603.312071 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97980.745314 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81111.111111 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 300000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74634.873061 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73913.183110 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130181.118043 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 93790.184063 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185674.188168 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 136198.763983 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156774.687944 # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 148207.955674 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133317.520186 # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 142514.596388 # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 167558.042207 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63803.921569 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 134904.247671 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 150376.849989 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 37974 # Transaction distribution
system.membus.trans_dist::ReadResp 209076 # Transaction distribution
system.membus.trans_dist::WriteReq 30901 # Transaction distribution
system.membus.trans_dist::WriteResp 30901 # Transaction distribution
system.membus.trans_dist::Writeback 136827 # Transaction distribution
system.membus.trans_dist::CleanEvict 16300 # Transaction distribution
system.membus.trans_dist::UpgradeReq 76178 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 40718 # Transaction distribution
system.membus.trans_dist::UpgradeResp 13724 # Transaction distribution
system.membus.trans_dist::ReadExReq 39427 # Transaction distribution
system.membus.trans_dist::ReadExResp 19516 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 171103 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663947 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 785587 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 894521 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18671220 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 18861706 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21179850 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 123655 # Total snoops (count)
system.membus.snoop_fanout::samples 585907 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 585907 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 585907 # Request fanout histogram
system.membus.reqLayer0.occupancy 81623000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 11432490 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 989982724 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1127040159 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 64467297 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.toL2Bus.trans_dist::ReadReq 37978 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 489550 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 30901 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 30901 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 364752 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 88216 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 79213 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 41051 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 120264 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 29 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 50507 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 50507 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 451588 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1086474 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 331144 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 1417618 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32384412 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5153902 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 37538314 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 454329 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 1220605 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 1.166616 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.372633 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 1017233 83.34% 83.34% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 203372 16.66% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 1220605 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 824158889 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 620803562 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 245897316 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2769 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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