240 lines
26 KiB
Plaintext
240 lines
26 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2134538 # Simulator instruction rate (inst/s)
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host_mem_usage 246068 # Number of bytes of host memory used
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host_seconds 941.18 # Real time elapsed on the host
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host_tick_rate 2989292617 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 2008987605 # Number of instructions simulated
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sim_seconds 2.813468 # Number of seconds simulated
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sim_ticks 2813467842000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454 # average ReadReq mshr miss latency
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system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_latency 79658418000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 75283842000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 3815994000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 3600138000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency 54553.304787 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 83474412000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_latency 78883980000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy
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system.cpu.dcache.occ_blocks::0 4095.204626 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency 54553.304787 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 720334778 # number of overall hits
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system.cpu.dcache.overall_miss_latency 83474412000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
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system.cpu.dcache.overall_misses 1530144 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_latency 78883980000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.replacements 1526048 # number of replacements
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system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.tagsinuse 4095.204626 # Cycle average of tags in use
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system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 1049839000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 107612 # number of writebacks
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system.cpu.dtb.data_accesses 722298387 # DTB accesses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_hits 721864922 # DTB hits
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system.cpu.dtb.data_misses 433465 # DTB misses
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.read_accesses 511488910 # DTB read accesses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_hits 511070026 # DTB read hits
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system.cpu.dtb.read_misses 418884 # DTB read misses
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system.cpu.dtb.write_accesses 210809477 # DTB write accesses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_hits 210794896 # DTB write hits
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system.cpu.dtb.write_misses 14581 # DTB write misses
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system.cpu.icache.ReadReq_accesses 2009421071 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_avg_miss_latency 23421.857305 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 2009410475 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 248178000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_latency 216390000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses 2009421071 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency 23421.857305 # average overall miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
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system.cpu.icache.demand_hits 2009410475 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 248178000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
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system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency 216390000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
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system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.occ_%::0 0.721886 # Average percentage of cache occupancy
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system.cpu.icache.occ_blocks::0 1478.423269 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_hits 2009410475 # number of overall hits
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system.cpu.icache.overall_miss_latency 248178000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
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system.cpu.icache.overall_misses 10596 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_latency 216390000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.replacements 9046 # number of replacements
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system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.tagsinuse 1478.423269 # Cycle average of tags in use
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system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.fetch_accesses 2009421176 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_hits 2009421071 # ITB hits
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system.cpu.itb.fetch_misses 105 # ITB misses
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_hits 5079 # number of ReadExReq hits
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system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_hits 55846 # number of ReadReq hits
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system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.Writeback_hits 107612 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_refs 0.041938 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses
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system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::0 0.880371 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_%::1 0.094050 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_blocks::0 28848.012979 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 3081.828747 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_hits 60925 # number of overall hits
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system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles
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system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses
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system.cpu.l2cache.overall_misses 1479815 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.replacements 1479797 # number of replacements
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system.cpu.l2cache.sampled_refs 1512480 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.tagsinuse 31929.841726 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 63431 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.writebacks 66898 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 5626935684 # number of cpu cycles simulated
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system.cpu.num_insts 2008987605 # Number of instructions executed
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system.cpu.num_refs 722298387 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
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---------- End Simulation Statistics ----------
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