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gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
Nilay Vaish 42fe2df354 stats: x86: updates due to change in div latency
2015-04-29 22:35:23 -05:00

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---------- Begin Simulation Statistics ----------
sim_seconds 5.133731 # Number of seconds simulated
sim_ticks 5133731116500 # Number of ticks simulated
final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 201130 # Simulator instruction rate (inst/s)
host_op_rate 399856 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 4230291451 # Simulator tick rate (ticks/s)
host_mem_usage 1019904 # Number of bytes of host memory used
host_seconds 1213.56 # Real time elapsed on the host
sim_insts 244084329 # Number of instructions simulated
sim_ops 485251122 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 445760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 5319424 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 180800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1995776 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 334336 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 3134080 # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::total 11441152 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 445760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 180800 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 334336 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 960896 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 9198080 # Number of bytes written to this memory
system.physmem.bytes_written::total 9198080 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 6965 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 83116 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2825 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 31184 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 5224 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 48970 # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 178768 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 143720 # Number of write requests responded to by this memory
system.physmem.num_writes::total 143720 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 86830 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 1036171 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 35218 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 388757 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 65125 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 610488 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2228623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 86830 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 35218 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 65125 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 187173 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1791695 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1791695 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1791695 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 86830 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1036171 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 35218 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 388757 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 65125 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 610488 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide 5523 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4020318 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 88682 # Number of read requests accepted
system.physmem.writeReqs 112966 # Number of write requests accepted
system.physmem.readBursts 88682 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 112966 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 5672000 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 3648 # Total number of bytes read from write queue
system.physmem.bytesWritten 6262656 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 5675648 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7229824 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 57 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 15112 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 1053 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 5542 # Per bank write bursts
system.physmem.perBankRdBursts::1 5155 # Per bank write bursts
system.physmem.perBankRdBursts::2 5253 # Per bank write bursts
system.physmem.perBankRdBursts::3 5290 # Per bank write bursts
system.physmem.perBankRdBursts::4 5356 # Per bank write bursts
system.physmem.perBankRdBursts::5 4920 # Per bank write bursts
system.physmem.perBankRdBursts::6 5387 # Per bank write bursts
system.physmem.perBankRdBursts::7 5003 # Per bank write bursts
system.physmem.perBankRdBursts::8 5335 # Per bank write bursts
system.physmem.perBankRdBursts::9 5304 # Per bank write bursts
system.physmem.perBankRdBursts::10 5486 # Per bank write bursts
system.physmem.perBankRdBursts::11 5354 # Per bank write bursts
system.physmem.perBankRdBursts::12 5802 # Per bank write bursts
system.physmem.perBankRdBursts::13 6837 # Per bank write bursts
system.physmem.perBankRdBursts::14 6164 # Per bank write bursts
system.physmem.perBankRdBursts::15 6437 # Per bank write bursts
system.physmem.perBankWrBursts::0 6158 # Per bank write bursts
system.physmem.perBankWrBursts::1 6179 # Per bank write bursts
system.physmem.perBankWrBursts::2 6254 # Per bank write bursts
system.physmem.perBankWrBursts::3 6080 # Per bank write bursts
system.physmem.perBankWrBursts::4 5432 # Per bank write bursts
system.physmem.perBankWrBursts::5 5660 # Per bank write bursts
system.physmem.perBankWrBursts::6 6180 # Per bank write bursts
system.physmem.perBankWrBursts::7 5898 # Per bank write bursts
system.physmem.perBankWrBursts::8 5226 # Per bank write bursts
system.physmem.perBankWrBursts::9 5788 # Per bank write bursts
system.physmem.perBankWrBursts::10 6663 # Per bank write bursts
system.physmem.perBankWrBursts::11 6618 # Per bank write bursts
system.physmem.perBankWrBursts::12 6477 # Per bank write bursts
system.physmem.perBankWrBursts::13 6666 # Per bank write bursts
system.physmem.perBankWrBursts::14 5929 # Per bank write bursts
system.physmem.perBankWrBursts::15 6646 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 21 # Number of times write queue was full causing retry
system.physmem.totGap 5132592336000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 88682 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 112966 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 81919 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 5154 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1007 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 209 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 47 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 38 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 61 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 58 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 54 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 52 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 51 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1123 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1363 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 3421 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3754 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4037 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 3921 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 4080 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 4330 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 4535 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 4412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 4362 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 5377 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 5007 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 4290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 6323 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 4956 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 4558 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 4427 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 1157 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 749 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 961 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 1599 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1755 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1610 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1553 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1348 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1351 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1565 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 976 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 909 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 681 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 485 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 217 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 121 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 93 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 102 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 66 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 24 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 40590 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 294.012121 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 173.528709 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 319.654231 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 15917 39.21% 39.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 9832 24.22% 63.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 4000 9.85% 73.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 2295 5.65% 78.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1624 4.00% 82.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1126 2.77% 85.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 717 1.77% 87.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 617 1.52% 89.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 4462 10.99% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 40590 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 3784 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.420983 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 192.521538 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 3781 99.92% 99.92% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 3784 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 3784 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 25.859937 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 18.216089 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 44.163335 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-15 82 2.17% 2.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-31 3425 90.51% 92.68% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-47 68 1.80% 94.48% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-63 12 0.32% 94.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-79 7 0.18% 94.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-95 15 0.40% 95.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-111 10 0.26% 95.64% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-127 22 0.58% 96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-143 22 0.58% 96.80% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-159 17 0.45% 97.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-175 6 0.16% 97.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-191 22 0.58% 97.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-207 36 0.95% 98.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-223 7 0.18% 99.13% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::224-239 2 0.05% 99.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::272-287 3 0.08% 99.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-303 1 0.03% 99.29% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::304-319 1 0.03% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-335 5 0.13% 99.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::336-351 4 0.11% 99.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::352-367 6 0.16% 99.71% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::368-383 5 0.13% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::480-495 1 0.03% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::512-527 1 0.03% 99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::528-543 1 0.03% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::544-559 1 0.03% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::560-575 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 3784 # Writes before turning the bus around for reads
system.physmem.totQLat 1019929900 # Total ticks spent queuing
system.physmem.totMemAccLat 2681648650 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 443125000 # Total ticks spent in databus transfers
system.physmem.avgQLat 11508.38 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30258.38 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.22 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.41 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 11.85 # Average write queue length when enqueuing
system.physmem.readRowHits 70792 # Number of row buffer hits during reads
system.physmem.writeRowHits 75088 # Number of row buffer hits during writes
system.physmem.readRowHitRate 79.88 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.73 # Row buffer hit rate for writes
system.physmem.avgGap 25453227.09 # Average gap between requests
system.physmem.pageHitRate 78.23 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 147351960 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 80169375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 326866800 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 309938400 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 94629197520 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 2236697889750 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 2582234091885 # Total energy per rank (pJ)
system.physmem_0.averagePower 667.903813 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 3683333970938 # Time in different power states
system.physmem_0.memoryStateTime::REF 127833680000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 17533181312 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 159410160 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 86781750 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 364408200 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 323974080 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 250042678080 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 95188577850 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 2235010334250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 2581176164370 # Total energy per rank (pJ)
system.physmem_1.averagePower 667.974824 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 3682508953468 # Time in different power states
system.physmem_1.memoryStateTime::REF 127833680000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 18355082532 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu0.numCycles 819384850 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 70809878 # Number of instructions committed
system.cpu0.committedOps 144569383 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 132504639 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 914830 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 14060186 # number of instructions that are conditional controls
system.cpu0.num_int_insts 132504639 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
system.cpu0.num_int_register_reads 242769596 # number of times the integer registers were read
system.cpu0.num_int_register_writes 113987635 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu0.num_cc_register_reads 82531896 # number of times the CC registers were read
system.cpu0.num_cc_register_writes 55153606 # number of times the CC registers were written
system.cpu0.num_mem_refs 13358556 # number of memory refs
system.cpu0.num_load_insts 9930193 # Number of load instructions
system.cpu0.num_store_insts 3428363 # Number of store instructions
system.cpu0.num_idle_cycles 778171794.138464 # Number of idle cycles
system.cpu0.num_busy_cycles 41213055.861536 # Number of busy cycles
system.cpu0.not_idle_fraction 0.050298 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.949702 # Percentage of idle cycles
system.cpu0.Branches 15315720 # Number of branches fetched
system.cpu0.op_class::No_OpClass 88912 0.06% 0.06% # Class of executed instruction
system.cpu0.op_class::IntAlu 131019698 90.63% 90.69% # Class of executed instruction
system.cpu0.op_class::IntMult 57722 0.04% 90.73% # Class of executed instruction
system.cpu0.op_class::IntDiv 46561 0.03% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatCvt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatMult 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatDiv 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::FloatSqrt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdAdd 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdAlu 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdCmp 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdCvt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdMisc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdMult 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdShift 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdSqrt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.76% # Class of executed instruction
system.cpu0.op_class::MemRead 9928558 6.87% 97.63% # Class of executed instruction
system.cpu0.op_class::MemWrite 3428363 2.37% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::total 144569814 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu0.dcache.tags.replacements 1636339 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.999246 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 19643358 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 1636851 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 12.000700 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 232.510577 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 255.541861 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.946808 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.454122 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.499105 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.046771 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 88441515 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 88441515 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 4745925 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 2412981 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4334563 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 11493469 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 3299103 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1688891 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 3099986 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 8087980 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19676 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 9874 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 30514 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 60064 # number of SoftPFReq hits
system.cpu0.dcache.demand_hits::cpu0.data 8045028 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 4101872 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 7434549 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 19581449 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 8064704 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 4111746 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 7465063 # number of overall hits
system.cpu0.dcache.overall_hits::total 19641513 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 345343 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 160729 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 822143 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 1328215 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 125592 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 64251 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 135437 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 325280 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145872 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 63796 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196481 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 406149 # number of SoftPFReq misses
system.cpu0.dcache.demand_misses::cpu0.data 470935 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 224980 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 957580 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1653495 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 616807 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 288776 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 1154061 # number of overall misses
system.cpu0.dcache.overall_misses::total 2059644 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2230470250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12318599402 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 14549069652 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2662717793 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4381161307 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 7043879100 # number of WriteReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 4893188043 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 16699760709 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 21592948752 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 4893188043 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 16699760709 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 21592948752 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 5091268 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 2573710 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 5156706 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 12821684 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 3424695 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1753142 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 3235423 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 8413260 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165548 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73670 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226995 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 466213 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 8515963 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 4326852 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 8392129 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 21234944 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 8681511 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 4400522 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 8619124 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 21701157 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067830 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.062450 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159432 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.103591 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036672 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.036649 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041861 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.038663 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.881146 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865970 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.865574 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871166 # miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055300 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.051996 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114105 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.077867 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071048 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.065623 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.133895 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.094909 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13877.211020 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14983.524037 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10953.851336 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41442.433472 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32348.333963 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 21654.817696 # average WriteReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21749.435697 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17439.546261 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 13058.974325 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16944.580031 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14470.431553 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 10483.825725 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 172709 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 19385 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.909414 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1546428 # number of writebacks
system.cpu0.dcache.writebacks::total 1546428 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 54 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 384012 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 384066 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1567 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32068 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 33635 # number of WriteReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu1.data 1621 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 416080 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 417701 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu1.data 1621 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 416080 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 417701 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 160675 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 438131 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 598806 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62684 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 103369 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 166053 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 63795 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 193085 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 256880 # number of SoftPFReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 223359 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 541500 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 764859 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2470174689 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3635352900 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6105527589 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 932249000 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770809752 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3703058752 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4458692939 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9348693664 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 13807386603 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5390941939 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12119503416 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 17510445355 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30496812500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33031149000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63527961500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 600115500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 761942500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1362058000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31096928000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33793091500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64890019500 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.062429 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084963 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046703 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.035755 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031949 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019737 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865956 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850613 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.550993 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.051622 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.064525 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.036019 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065255 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.085227 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.047082 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12376.027696 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13040.256827 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12862.027124 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39406.781459 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35168.695644 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36768.547325 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14613.198527 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14350.207173 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14415.519900 # average SoftPFReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19962.002601 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17264.438899 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18052.198644 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 871419 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 127964014 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 871931 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 146.759335 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 150504235000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 260.667168 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 143.237667 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.336510 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.509116 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.279761 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.207688 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.996565 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 303 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 129734477 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 129734477 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 86118928 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 38597787 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3247299 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 127964014 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 86118928 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 38597787 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3247299 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 127964014 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 86118928 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 38597787 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3247299 # number of overall hits
system.cpu0.icache.overall_hits::total 127964014 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 294029 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 171033 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 433450 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 898512 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 294029 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 171033 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 433450 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 898512 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 294029 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 171033 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 433450 # number of overall misses
system.cpu0.icache.overall_misses::total 898512 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2424026997 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5943573307 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 8367600304 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 2424026997 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 5943573307 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 8367600304 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 2424026997 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 5943573307 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 8367600304 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 86412957 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 38768820 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 3680749 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 128862526 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 86412957 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 38768820 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 3680749 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 128862526 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 86412957 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 38768820 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 3680749 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 128862526 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003403 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004412 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117761 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.006973 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003403 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004412 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117761 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.006973 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003403 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004412 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117761 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.006973 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14172.861360 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.246642 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 9312.730719 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 9312.730719 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14172.861360 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.246642 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 9312.730719 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 7161 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 313 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 22.878594 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 26561 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 26561 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 26561 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 26561 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 26561 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 26561 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 171033 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 406889 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 577922 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 171033 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 406889 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 577922 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 171033 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 406889 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 577922 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2166425503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5084799831 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 7251225334 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2166425503 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5084799831 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 7251225334 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2166425503 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5084799831 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 7251225334 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004485 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.004485 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004412 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110545 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.004485 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12547.065753 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12666.710535 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12496.773889 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12547.065753 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 2604016269 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 35221864 # Number of instructions committed
system.cpu1.committedOps 68477973 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 63543554 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 474559 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 6488284 # number of instructions that are conditional controls
system.cpu1.num_int_insts 63543554 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
system.cpu1.num_int_register_reads 117503426 # number of times the integer registers were read
system.cpu1.num_int_register_writes 54764358 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
system.cpu1.num_cc_register_reads 35994299 # number of times the CC registers were read
system.cpu1.num_cc_register_writes 26824776 # number of times the CC registers were written
system.cpu1.num_mem_refs 4585615 # number of memory refs
system.cpu1.num_load_insts 2831531 # Number of load instructions
system.cpu1.num_store_insts 1754084 # Number of store instructions
system.cpu1.num_idle_cycles 2478252415.347472 # Number of idle cycles
system.cpu1.num_busy_cycles 125763853.652528 # Number of busy cycles
system.cpu1.not_idle_fraction 0.048296 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.951704 # Percentage of idle cycles
system.cpu1.Branches 7131846 # Number of branches fetched
system.cpu1.op_class::No_OpClass 33642 0.05% 0.05% # Class of executed instruction
system.cpu1.op_class::IntAlu 63809884 93.18% 93.23% # Class of executed instruction
system.cpu1.op_class::IntMult 28068 0.04% 93.27% # Class of executed instruction
system.cpu1.op_class::IntDiv 22761 0.03% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatCvt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatMult 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatDiv 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::FloatSqrt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdAdd 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdAlu 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdCmp 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdCvt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdMisc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdMult 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdShift 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdSqrt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.31% # Class of executed instruction
system.cpu1.op_class::MemRead 2829816 4.13% 97.44% # Class of executed instruction
system.cpu1.op_class::MemWrite 1754084 2.56% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::total 68478255 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 29642945 # Number of BP lookups
system.cpu2.branchPred.condPredicted 29642945 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 342109 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 26793966 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 26087449 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 97.363149 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 617263 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 68240 # Number of incorrect RAS predictions.
system.cpu2.numCycles 154815215 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 11226493 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 146138571 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 29642945 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 26704712 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 142088964 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 715876 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 100355 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.MiscStallCycles 5095 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 9800 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 59006 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 22 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 1044 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 3680756 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 177933 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 3589 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 153848066 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.868751 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 3.040918 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 97905187 63.64% 63.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 902052 0.59% 64.22% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 23780045 15.46% 79.68% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 607949 0.40% 80.08% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 861058 0.56% 80.64% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 871308 0.57% 81.20% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 586027 0.38% 81.58% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 774714 0.50% 82.09% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 27559726 17.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 153848066 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.191473 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.943955 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 10308577 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 93114688 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 23867360 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 5032797 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 358589 # Number of cycles decode is squashing
system.cpu2.decode.DecodedInsts 284536277 # Number of instructions handled by decode
system.cpu2.rename.SquashCycles 358589 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 12446525 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 76456474 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 4505534 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 26483485 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 12431465 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 283232358 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 203213 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 5874103 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 62488 # Number of times rename has blocked due to LQ full
system.cpu2.rename.SQFullEvents 4343022 # Number of times rename has blocked due to SQ full
system.cpu2.rename.RenamedOperands 338256341 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 618855518 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 379959971 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 144 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 325490778 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 12765563 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 164991 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 166448 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 24511654 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6973831 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3905800 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 411343 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 337090 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 281177337 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 428187 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 278961410 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 111637 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 9401758 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 14188384 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 65116 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 153848066 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 1.813227 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 2.402216 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 90533816 58.85% 58.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 5362080 3.49% 62.33% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 3874219 2.52% 64.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 3850508 2.50% 67.35% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 22615321 14.70% 82.05% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 2805299 1.82% 83.88% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 24069627 15.65% 99.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 503741 0.33% 99.85% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 233455 0.15% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 153848066 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 1762451 85.95% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.95% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 222010 10.83% 96.78% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 66103 3.22% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 83756 0.03% 0.03% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 267874850 96.03% 96.06% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 60171 0.02% 96.08% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 55540 0.02% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 52 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.10% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 7279557 2.61% 98.71% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3607484 1.29% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 278961410 # Type of FU issued
system.cpu2.iq.rate 1.801899 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 2050564 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.007351 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 713932890 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 291011736 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 277302749 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 197 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 156 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 76 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 280928122 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 96 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 764231 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1280710 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 6256 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 5226 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 665708 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 750625 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 30616 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 358589 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 70562607 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 2840752 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 281605524 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 45396 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6973831 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3905800 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 251212 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 165628 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2346507 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 5226 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 195667 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 202777 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 398444 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 278332986 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 7126227 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 571848 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 0 # number of nop insts executed
system.cpu2.iew.exec_refs 10641796 # number of memory reference insts executed
system.cpu2.iew.exec_branches 28281444 # Number of branches executed
system.cpu2.iew.exec_stores 3515569 # Number of stores executed
system.cpu2.iew.exec_rate 1.797840 # Inst execution rate
system.cpu2.iew.wb_sent 278129863 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 277302825 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 216123267 # num instructions producing a value
system.cpu2.iew.wb_consumers 354504830 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 1.791186 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.609648 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 9397385 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 363071 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 345314 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 152442881 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 1.785612 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 2.660258 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 94319401 61.87% 61.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4425348 2.90% 64.77% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1302226 0.85% 65.63% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 24740165 16.23% 81.86% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 979797 0.64% 82.50% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 733746 0.48% 82.98% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 423992 0.28% 83.26% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 23324047 15.30% 98.56% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 2194159 1.44% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 152442881 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 138052587 # Number of instructions committed
system.cpu2.commit.committedOps 272203766 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8933213 # Number of memory references committed
system.cpu2.commit.loads 5693121 # Number of loads committed
system.cpu2.commit.membars 162094 # Number of memory barriers committed
system.cpu2.commit.branches 27859693 # Number of branches committed
system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 248852946 # Number of committed integer instructions.
system.cpu2.commit.function_calls 461863 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 49962 0.02% 0.02% # Class of committed instruction
system.cpu2.commit.op_class_0::IntAlu 263110099 96.66% 96.68% # Class of committed instruction
system.cpu2.commit.op_class_0::IntMult 57933 0.02% 96.70% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 52599 0.02% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.72% # Class of committed instruction
system.cpu2.commit.op_class_0::MemRead 5693065 2.09% 98.81% # Class of committed instruction
system.cpu2.commit.op_class_0::MemWrite 3240092 1.19% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::total 272203766 # Class of committed instruction
system.cpu2.commit.bw_lim_events 2194159 # number cycles where commit BW limit reached
system.cpu2.rob.rob_reads 431819572 # The number of ROB reads
system.cpu2.rob.rob_writes 564614589 # The number of ROB writes
system.cpu2.timesIdled 120593 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 967149 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 4904349916 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 138052587 # Number of Instructions Simulated
system.cpu2.committedOps 272203766 # Number of Ops (including micro ops) Simulated
system.cpu2.cpi 1.121422 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 1.121422 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.891725 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.891725 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 371027158 # number of integer regfile reads
system.cpu2.int_regfile_writes 222252306 # number of integer regfile writes
system.cpu2.fp_regfile_reads 72988 # number of floating regfile reads
system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes
system.cpu2.cc_regfile_reads 141449053 # number of cc regfile reads
system.cpu2.cc_regfile_writes 108603776 # number of cc regfile writes
system.cpu2.misc_regfile_reads 90794642 # number of misc regfile reads
system.cpu2.misc_regfile_writes 144161 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 3553347 # Transaction distribution
system.iobus.trans_dist::ReadResp 3553347 # Transaction distribution
system.iobus.trans_dist::WriteReq 57679 # Transaction distribution
system.iobus.trans_dist::WriteResp 10959 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.iobus.trans_dist::MessageReq 1698 # Transaction distribution
system.iobus.trans_dist::MessageResp 1698 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082616 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 7126806 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3396 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3396 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 7225448 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6660 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541308 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 3569512 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6792 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 6604072 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 2741680 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 28000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 6074000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 16000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 141309000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 285000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 86000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10492000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 155889253 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 301765000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 31644993 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer2.occupancy 1151000 # Layer occupancy (ticks)
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 47568 # number of replacements
system.iocache.tags.tagsinuse 0.079964 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 5000587823009 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079964 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004998 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.004998 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 428607 # Number of tag accesses
system.iocache.tags.data_accesses 428607 # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses
system.iocache.demand_misses::total 903 # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses
system.iocache.overall_misses::total 903 # number of overall misses
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 128377230 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 128377230 # number of ReadReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 5164742030 # number of WriteInvalidateReq miss cycles
system.iocache.WriteInvalidateReq_miss_latency::total 5164742030 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::pc.south_bridge.ide 128377230 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 128377230 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::pc.south_bridge.ide 128377230 # number of overall miss cycles
system.iocache.overall_miss_latency::total 128377230 # number of overall miss cycles
system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 142167.475083 # average ReadReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 110546.704409 # average WriteInvalidateReq miss latency
system.iocache.WriteInvalidateReq_avg_miss_latency::total 110546.704409 # average WriteInvalidateReq miss latency
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 142167.475083 # average overall miss latency
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 142167.475083 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 142167.475083 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 17612 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 2632 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 6.691489 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 801 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28264 # number of WriteInvalidateReq MSHR misses
system.iocache.WriteInvalidateReq_mshr_misses::total 28264 # number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::pc.south_bridge.ide 801 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::pc.south_bridge.ide 801 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 801 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 86423212 # number of ReadReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 3695010034 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3695010034 # number of WriteInvalidateReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 86423212 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86423212 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 86423212 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 0.887043 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.604966 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.604966 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 0.887043 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.887043 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 0.887043 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 107894.147316 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130732.027809 # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130732.027809 # average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 107894.147316 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 107894.147316 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 105369 # number of replacements
system.l2c.tags.tagsinuse 64830.626845 # Cycle average of tags in use
system.l2c.tags.total_refs 3705679 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 169446 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 21.869380 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 50858.096780 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134526 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 1601.427587 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 5289.246768 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000914 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 232.896636 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 1549.888722 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.632040 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1227.720144 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 4063.582728 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.776033 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.024436 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.080708 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.003554 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.023649 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000116 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.018734 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.062005 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.989237 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1024 64077 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 4057 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 8155 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 51563 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.977737 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 33969935 # Number of tag accesses
system.l2c.tags.data_accesses 33969935 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 19552 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 10769 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 287050 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 476755 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 13141 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 7558 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 168208 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 219838 # number of ReadReq hits
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system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 385025750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1049073500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 1960621999 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5213239 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10949612 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 16162851 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1688636313 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2360590135 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 4049226448 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 193782500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 2018673563 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 385025750 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 3409663635 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 6009848447 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 193782500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 2018673563 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2632999 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 385025750 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 3409663635 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 6009848447 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27827045500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30156785500 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 57983831000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 554838500 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 711575000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 1266413500 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28381884000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30868360500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 59250244500 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.020635 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.022154 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.011365 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.843854 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.864789 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.519139 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430195 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.344148 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.214415 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.033676 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000076 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.016517 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.109717 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000528 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012840 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.067214 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.033676 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71251.565199 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 75024.923121 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 73431.535543 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20524.562992 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17833.244300 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18620.796083 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62910.226995 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66788.992050 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 65114.759721 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68595.575221 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64137.814164 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75228.542857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 5117226 # Transaction distribution
system.membus.trans_dist::ReadResp 5117226 # Transaction distribution
system.membus.trans_dist::WriteReq 13905 # Transaction distribution
system.membus.trans_dist::WriteResp 13905 # Transaction distribution
system.membus.trans_dist::Writeback 143720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
system.membus.trans_dist::UpgradeReq 1707 # Transaction distribution
system.membus.trans_dist::UpgradeResp 1707 # Transaction distribution
system.membus.trans_dist::ReadExReq 130847 # Transaction distribution
system.membus.trans_dist::ReadExResp 130847 # Transaction distribution
system.membus.trans_dist::MessageReq 1698 # Transaction distribution
system.membus.trans_dist::MessageResp 1698 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3396 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total 3396 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126806 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3037388 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457961 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 10622155 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141555 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141555 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 10767106 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6792 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6792 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569512 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6074773 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17637504 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 27281789 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6011648 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 820 # Total snoops (count)
system.membus.snoop_fanout::samples 372049 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::1 372049 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 372049 # Request fanout histogram
system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 2302000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer3.occupancy 670380805 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1151000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 1321113701 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 32422007 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 29 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.toL2Bus.trans_dist::ReadReq 7449528 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 7448995 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 13907 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 13907 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1546428 # Transaction distribution
system.toL2Bus.trans_dist::WriteInvalidateReq 28278 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1672 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 225048 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17030802 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55802432 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213393597 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 72565 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 4266300 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 3.011166 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.105077 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::3 4218663 98.88% 98.88% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 47637 1.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 4266300 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 868906655 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1944011740 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 26208491 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 98848126 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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