bf2f178f85
This patch adds DRAMSim2 as a memory controller by wrapping the external library and creating a sublass of AbstractMemory that bridges between the semantics of gem5 and the DRAMSim2 interface. The DRAMSim2 wrapper extracts the clock period from the config file. There is no way of extracting this information from DRAMSim2 itself, so we simply read the same config file and get it from there. To properly model the response queue, the wrapper keeps track of how many transactions are in the actual controller, and how many are stacking up waiting to be sent back as responses (in the wrapper). The latter requires us to move away from the queued port and manage the packets ourselves. This is due to DRAMSim2 not having any flow control on the response path. DRAMSim2 assumes that the transactions it is given are matching the burst size of the choosen memory. The wrapper checks to ensure the cache line size of the system matches the burst size of DRAMSim2 as there are currently no provisions to split the system requests. In theory we could allow a cache line size smaller than the burst size, but that would lead to inefficient use of the DRAM, so for not we fatal also in this case.
411 lines
12 KiB
C++
411 lines
12 KiB
C++
/*
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* Copyright (c) 2013 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Andreas Hansson
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*/
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#include "DRAMSim2/Callback.h"
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#include "base/callback.hh"
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#include "base/trace.hh"
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#include "debug/DRAMSim2.hh"
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#include "debug/Drain.hh"
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#include "mem/dramsim2.hh"
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#include "sim/system.hh"
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DRAMSim2::DRAMSim2(const Params* p) :
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AbstractMemory(p),
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port(name() + ".port", *this),
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wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
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p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
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retryReq(false), retryResp(false),
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nbrOutstandingReads(0), nbrOutstandingWrites(0),
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drainManager(NULL),
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sendResponseEvent(this), tickEvent(this)
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{
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DPRINTF(DRAMSim2,
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"Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
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wrapper.clockPeriod(), wrapper.queueSize());
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DRAMSim::TransactionCompleteCB* read_cb =
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new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
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this, &DRAMSim2::readComplete);
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DRAMSim::TransactionCompleteCB* write_cb =
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new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
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this, &DRAMSim2::writeComplete);
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wrapper.setCallbacks(read_cb, write_cb);
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// Register a callback to compensate for the destructor not
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// being called. The callback prints the DRAMSim2 stats.
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Callback* cb = new MakeCallback<DRAMSim2Wrapper,
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&DRAMSim2Wrapper::printStats>(wrapper);
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registerExitCallback(cb);
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}
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void
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DRAMSim2::init()
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{
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if (!port.isConnected()) {
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fatal("DRAMSim2 %s is unconnected!\n", name());
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} else {
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port.sendRangeChange();
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}
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if (system()->cacheLineSize() != wrapper.burstSize())
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fatal("DRAMSim2 burst size %d does not match cache line size %d\n",
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wrapper.burstSize(), system()->cacheLineSize());
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}
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void
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DRAMSim2::startup()
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{
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// kick off the clock ticks
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schedule(tickEvent, clockEdge());
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}
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void
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DRAMSim2::sendResponse()
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{
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assert(!retryResp);
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assert(!responseQueue.empty());
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DPRINTF(DRAMSim2, "Attempting to send response\n");
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bool success = port.sendTimingResp(responseQueue.front());
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if (success) {
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responseQueue.pop_front();
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DPRINTF(DRAMSim2, "Have %d read, %d write, %d responses outstanding\n",
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nbrOutstandingReads, nbrOutstandingWrites,
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responseQueue.size());
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if (!responseQueue.empty() && !sendResponseEvent.scheduled())
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schedule(sendResponseEvent, curTick());
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// check if we were asked to drain and if we are now done
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if (drainManager && nbrOutstanding() == 0) {
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drainManager->signalDrainDone();
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drainManager = NULL;
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}
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} else {
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retryResp = true;
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DPRINTF(DRAMSim2, "Waiting for response retry\n");
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assert(!sendResponseEvent.scheduled());
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}
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}
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unsigned int
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DRAMSim2::nbrOutstanding() const
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{
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return nbrOutstandingReads + nbrOutstandingWrites + responseQueue.size();
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}
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void
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DRAMSim2::tick()
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{
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wrapper.tick();
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// is the connected port waiting for a retry, if so check the
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// state and send a retry if conditions have changed
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if (retryReq && nbrOutstanding() < wrapper.queueSize()) {
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retryReq = false;
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port.sendRetry();
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}
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schedule(tickEvent, curTick() + wrapper.clockPeriod() * SimClock::Int::ns);
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}
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Tick
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DRAMSim2::recvAtomic(PacketPtr pkt)
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{
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access(pkt);
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// 50 ns is just an arbitrary value at this point
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return pkt->memInhibitAsserted() ? 0 : 50000;
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}
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void
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DRAMSim2::recvFunctional(PacketPtr pkt)
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{
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pkt->pushLabel(name());
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functionalAccess(pkt);
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// potentially update the packets in our response queue as well
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for (auto i = responseQueue.begin(); i != responseQueue.end(); ++i)
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pkt->checkFunctional(*i);
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pkt->popLabel();
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}
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bool
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DRAMSim2::recvTimingReq(PacketPtr pkt)
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{
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// we should never see a new request while in retry
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assert(!retryReq);
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// @todo temporary hack to deal with memory corruption issues until
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// 4-phase transactions are complete
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for (int x = 0; x < pendingDelete.size(); x++)
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delete pendingDelete[x];
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pendingDelete.clear();
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if (pkt->memInhibitAsserted()) {
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// snooper will supply based on copy of packet
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// still target's responsibility to delete packet
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pendingDelete.push_back(pkt);
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return true;
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}
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// if we cannot accept we need to send a retry once progress can
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// be made
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bool can_accept = nbrOutstanding() < wrapper.queueSize();
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// keep track of the transaction
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if (pkt->isRead()) {
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if (can_accept) {
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outstandingReads[pkt->getAddr()].push(pkt);
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// we count a transaction as outstanding until it has left the
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// queue in the controller, and the response has been sent
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// back, note that this will differ for reads and writes
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++nbrOutstandingReads;
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}
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} else if (pkt->isWrite()) {
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if (can_accept) {
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outstandingWrites[pkt->getAddr()].push(pkt);
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++nbrOutstandingWrites;
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// perform the access for writes
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accessAndRespond(pkt);
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}
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} else {
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// keep it simple and just respond if necessary
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accessAndRespond(pkt);
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return true;
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}
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if (can_accept) {
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// we should never have a situation when we think there is space,
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// and there isn't
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assert(wrapper.canAccept());
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DPRINTF(DRAMSim2, "Enqueueing address %lld\n", pkt->getAddr());
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// @todo what about the granularity here, implicit assumption that
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// a transaction matches the burst size of the memory (which we
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// cannot determine without parsing the ini file ourselves)
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wrapper.enqueue(pkt->isWrite(), pkt->getAddr());
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return true;
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} else {
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retryReq = true;
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return false;
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}
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}
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void
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DRAMSim2::recvRetry()
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{
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DPRINTF(DRAMSim2, "Retrying\n");
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assert(retryResp);
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retryResp = false;
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sendResponse();
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}
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void
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DRAMSim2::accessAndRespond(PacketPtr pkt)
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{
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DPRINTF(DRAMSim2, "Access for address %lld\n", pkt->getAddr());
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bool needsResponse = pkt->needsResponse();
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// do the actual memory access which also turns the packet into a
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// response
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access(pkt);
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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// access already turned the packet into a response
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assert(pkt->isResponse());
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// @todo someone should pay for this
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pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
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DPRINTF(DRAMSim2, "Queuing response for address %lld\n",
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pkt->getAddr());
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// queue it to be sent back
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responseQueue.push_back(pkt);
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// if we are not already waiting for a retry, or are scheduled
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// to send a response, schedule an event
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if (!retryResp && !sendResponseEvent.scheduled())
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schedule(sendResponseEvent, curTick());
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} else {
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// @todo the packet is going to be deleted, and the DRAMPacket
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// is still having a pointer to it
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pendingDelete.push_back(pkt);
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}
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}
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void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
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{
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assert(cycle == divCeil(curTick(),
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wrapper.clockPeriod() * SimClock::Int::ns));
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DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
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// get the outstanding reads for the address in question
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auto p = outstandingReads.find(addr);
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assert(p != outstandingReads.end());
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// first in first out, which is not necessarily true, but it is
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// the best we can do at this point
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PacketPtr pkt = p->second.front();
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p->second.pop();
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if (p->second.empty())
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outstandingReads.erase(p);
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// no need to check for drain here as the next call will add a
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// response to the response queue straight away
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assert(nbrOutstandingReads != 0);
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--nbrOutstandingReads;
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// perform the actual memory access
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accessAndRespond(pkt);
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}
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void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
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{
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assert(cycle == divCeil(curTick(),
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wrapper.clockPeriod() * SimClock::Int::ns));
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DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
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// get the outstanding reads for the address in question
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auto p = outstandingWrites.find(addr);
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assert(p != outstandingWrites.end());
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// we have already responded, and this is only to keep track of
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// what is outstanding
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p->second.pop();
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if (p->second.empty())
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outstandingWrites.erase(p);
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assert(nbrOutstandingWrites != 0);
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--nbrOutstandingWrites;
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// check if we were asked to drain and if we are now done
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if (drainManager && nbrOutstanding() == 0) {
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drainManager->signalDrainDone();
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drainManager = NULL;
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}
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}
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BaseSlavePort&
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DRAMSim2::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name != "port") {
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return MemObject::getSlavePort(if_name, idx);
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} else {
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return port;
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}
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}
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unsigned int
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DRAMSim2::drain(DrainManager* dm)
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{
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// check our outstanding reads and writes and if any they need to
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// drain
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if (nbrOutstanding() != 0) {
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setDrainState(Drainable::Draining);
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drainManager = dm;
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return 1;
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} else {
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setDrainState(Drainable::Drained);
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return 0;
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}
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}
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DRAMSim2::MemoryPort::MemoryPort(const std::string& _name,
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DRAMSim2& _memory)
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: SlavePort(_name, &_memory), memory(_memory)
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{ }
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AddrRangeList
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DRAMSim2::MemoryPort::getAddrRanges() const
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{
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AddrRangeList ranges;
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ranges.push_back(memory.getAddrRange());
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return ranges;
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}
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Tick
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DRAMSim2::MemoryPort::recvAtomic(PacketPtr pkt)
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{
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return memory.recvAtomic(pkt);
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}
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void
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DRAMSim2::MemoryPort::recvFunctional(PacketPtr pkt)
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{
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memory.recvFunctional(pkt);
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}
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bool
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DRAMSim2::MemoryPort::recvTimingReq(PacketPtr pkt)
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{
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// pass it to the memory controller
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return memory.recvTimingReq(pkt);
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}
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void
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DRAMSim2::MemoryPort::recvRetry()
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{
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memory.recvRetry();
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}
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DRAMSim2*
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DRAMSim2Params::create()
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{
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return new DRAMSim2(this);
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}
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