937 lines
30 KiB
C++
937 lines
30 KiB
C++
/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_BASE_DYN_INST_HH__
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#define __CPU_BASE_DYN_INST_HH__
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#include <bitset>
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#include <list>
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#include <string>
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#include "arch/faults.hh"
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#include "base/fast_alloc.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/op_class.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "sim/system.hh"
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/**
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* @file
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* Defines a dynamic instruction context.
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*/
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// Forward declaration.
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class StaticInstPtr;
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template <class Impl>
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class BaseDynInst : public FastAlloc, public RefCounted
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{
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public:
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// Typedef for the CPU.
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typedef typename Impl::CPUType ImplCPU;
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typedef typename ImplCPU::ImplState ImplState;
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// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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// Integer register type.
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typedef TheISA::IntReg IntReg;
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// Floating point register type.
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typedef TheISA::FloatReg FloatReg;
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// The DynInstPtr type.
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typedef typename Impl::DynInstPtr DynInstPtr;
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// The list of instructions iterator type.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs, /// Max dest regs
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};
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/** The StaticInst used by this BaseDynInst. */
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StaticInstPtr staticInst;
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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/** InstRecord that tracks this instructions. */
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Trace::InstRecord *traceData;
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/**
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* Does a read to a given address.
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* @param addr The address to read.
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* @param data The read's data is written into this parameter.
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* @param flags The request's flags.
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* @return Returns any fault due to the read.
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*/
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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/**
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* Does a write to a given address.
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* @param data The data to be written.
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* @param addr The address to write to.
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* @param flags The request's flags.
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* @param res The result of the write (for load locked/store conditionals).
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* @return Returns any fault due to the write.
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*/
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template <class T>
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res);
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void prefetch(Addr addr, unsigned flags);
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void writeHint(Addr addr, int size, unsigned flags);
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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/** @todo: Consider making this private. */
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public:
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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enum Status {
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IqEntry, /// Instruction is in the IQ
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RobEntry, /// Instruction is in the ROB
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LsqEntry, /// Instruction is in the LSQ
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Completed, /// Instruction has completed
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ResultReady, /// Instruction has its result
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CanIssue, /// Instruction can issue and execute
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Issued, /// Instruction has issued
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Executed, /// Instruction has executed
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CanCommit, /// Instruction can commit
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AtCommit, /// Instruction has reached commit
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Committed, /// Instruction has committed
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Squashed, /// Instruction is squashed
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SquashedInIQ, /// Instruction is squashed in the IQ
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SquashedInLSQ, /// Instruction is squashed in the LSQ
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SquashedInROB, /// Instruction is squashed in the ROB
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RecoverInst, /// Is a recover instruction
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BlockingInst, /// Is a blocking instruction
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ThreadsyncWait, /// Is a thread synchronization instruction
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SerializeBefore, /// Needs to serialize on
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/// instructions ahead of it
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SerializeAfter, /// Needs to serialize instructions behind it
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SerializeHandled, /// Serialization has been handled
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NumStatus
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};
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/** The status of this BaseDynInst. Several bits can be set. */
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std::bitset<NumStatus> status;
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/** The thread this instruction is from. */
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short threadNumber;
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/** data address space ID, for loads & stores. */
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short asid;
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/** How many source registers are ready. */
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unsigned readyRegs;
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/** Pointer to the Impl's CPU object. */
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ImplCPU *cpu;
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/** Pointer to the thread state. */
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ImplState *thread;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** Is the effective virtual address valid. */
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bool effAddrValid;
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/** The effective physical address. */
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Addr physEffAddr;
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/** Effective virtual address for a copy source. */
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Addr copySrcEffAddr;
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/** Effective physical address for a copy source. */
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Addr copySrcPhysEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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union Result {
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uint64_t integer;
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// float fp;
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double dbl;
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};
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/** The result of the instruction; assumes for now that there's only one
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* destination register.
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*/
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Result instResult;
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/** Records changes to result? */
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bool recordResult;
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/** PC of this instruction. */
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Addr PC;
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/** Micro PC of this instruction. */
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Addr microPC;
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protected:
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/** Next non-speculative PC. It is not filled in at fetch, but rather
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* once the target of the branch is truly known (either decode or
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* execute).
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*/
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Addr nextPC;
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/** Next non-speculative NPC. Target PC for Mips or Sparc. */
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Addr nextNPC;
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/** Next non-speculative micro PC. */
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Addr nextMicroPC;
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/** Predicted next PC. */
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Addr predPC;
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/** Predicted next NPC. */
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Addr predNPC;
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/** Predicted next microPC */
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Addr predMicroPC;
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/** If this is a branch that was predicted taken */
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bool predTaken;
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public:
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/** Count of total number of dynamic instructions. */
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static int instcount;
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#ifdef DEBUG
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void dumpSNList();
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#endif
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/** Whether or not the source register is ready.
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* @todo: Not sure this should be here vs the derived class.
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*/
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bool _readySrcRegIdx[MaxInstSrcRegs];
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protected:
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/** Flattened register index of the destination registers of this
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* instruction.
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*/
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TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
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/** Flattened register index of the source registers of this
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* instruction.
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*/
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TheISA::RegIndex _flatSrcRegIdx[TheISA::MaxInstSrcRegs];
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/** Physical register index of the destination registers of this
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* instruction.
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*/
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PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
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/** Physical register index of the source registers of this
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* instruction.
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*/
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PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
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/** Physical register index of the previous producers of the
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* architected destinations.
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*/
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PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
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public:
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/** Returns the physical register index of the i'th destination
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* register.
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*/
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PhysRegIndex renamedDestRegIdx(int idx) const
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{
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return _destRegIdx[idx];
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}
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/** Returns the physical register index of the i'th source register. */
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PhysRegIndex renamedSrcRegIdx(int idx) const
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{
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return _srcRegIdx[idx];
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}
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/** Returns the flattened register index of the i'th destination
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* register.
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*/
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TheISA::RegIndex flattenedDestRegIdx(int idx) const
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{
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return _flatDestRegIdx[idx];
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}
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/** Returns the flattened register index of the i'th source register */
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TheISA::RegIndex flattenedSrcRegIdx(int idx) const
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{
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return _flatSrcRegIdx[idx];
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}
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/** Returns the physical register index of the previous physical register
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* that remapped to the same logical register index.
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*/
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PhysRegIndex prevDestRegIdx(int idx) const
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{
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return _prevDestRegIdx[idx];
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}
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/** Renames a destination register to a physical register. Also records
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* the previous physical register that the logical register mapped to.
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*/
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void renameDestReg(int idx,
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PhysRegIndex renamed_dest,
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PhysRegIndex previous_rename)
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{
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_destRegIdx[idx] = renamed_dest;
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_prevDestRegIdx[idx] = previous_rename;
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}
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/** Renames a source logical register to the physical register which
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* has/will produce that logical register's result.
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* @todo: add in whether or not the source register is ready.
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*/
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void renameSrcReg(int idx, PhysRegIndex renamed_src)
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{
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_srcRegIdx[idx] = renamed_src;
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}
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/** Flattens a source architectural register index into a logical index.
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*/
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void flattenSrcReg(int idx, TheISA::RegIndex flattened_src)
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{
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_flatSrcRegIdx[idx] = flattened_src;
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}
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/** Flattens a destination architectural register index into a logical
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* index.
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*/
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void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
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{
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_flatDestRegIdx[idx] = flattened_dest;
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}
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/** BaseDynInst constructor given a binary instruction.
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* @param staticInst A StaticInstPtr to the underlying instruction.
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* @param PC The PC of the instruction.
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* @param pred_PC The predicted next PC.
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* @param pred_NPC The predicted next NPC.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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BaseDynInst(StaticInstPtr staticInst, Addr PC, Addr NPC, Addr microPC,
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Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
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InstSeqNum seq_num, ImplCPU *cpu);
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/** BaseDynInst constructor given a binary instruction.
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* @param inst The binary instruction.
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* @param PC The PC of the instruction.
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* @param pred_PC The predicted next PC.
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* @param pred_NPC The predicted next NPC.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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BaseDynInst(TheISA::ExtMachInst inst, Addr PC, Addr NPC, Addr microPC,
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Addr pred_PC, Addr pred_NPC, Addr pred_MicroPC,
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InstSeqNum seq_num, ImplCPU *cpu);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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*/
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BaseDynInst(StaticInstPtr &_staticInst);
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/** BaseDynInst destructor. */
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~BaseDynInst();
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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/** Dumps out contents of this BaseDynInst into given string. */
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void dump(std::string &outstring);
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/** Read this CPU's ID. */
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int readCpuId() { return cpu->readCpuId(); }
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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/** Checks whether or not this instruction has had its branch target
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* calculated yet. For now it is not utilized and is hacked to be
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* always false.
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* @todo: Actually use this instruction.
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*/
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bool doneTargCalc() { return false; }
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/** Returns the next PC. This could be the speculative next PC if it is
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* called prior to the actual branch target being calculated.
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*/
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Addr readNextPC() { return nextPC; }
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/** Returns the next NPC. This could be the speculative next NPC if it is
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* called prior to the actual branch target being calculated.
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*/
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Addr readNextNPC()
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{
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#if ISA_HAS_DELAY_SLOT
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return nextNPC;
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#else
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return nextPC + sizeof(TheISA::MachInst);
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#endif
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}
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Addr readNextMicroPC()
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{
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return nextMicroPC;
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}
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/** Set the predicted target of this current instruction. */
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void setPredTarg(Addr predicted_PC, Addr predicted_NPC,
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Addr predicted_MicroPC)
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{
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predPC = predicted_PC;
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predNPC = predicted_NPC;
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predMicroPC = predicted_MicroPC;
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}
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/** Returns the predicted PC immediately after the branch. */
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Addr readPredPC() { return predPC; }
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/** Returns the predicted PC two instructions after the branch */
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Addr readPredNPC() { return predNPC; }
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/** Returns the predicted micro PC after the branch */
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Addr readPredMicroPC() { return predMicroPC; }
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/** Returns whether the instruction was predicted taken or not. */
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bool readPredTaken()
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{
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return predTaken;
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}
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void setPredTaken(bool predicted_taken)
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{
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predTaken = predicted_taken;
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}
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/** Returns whether the instruction mispredicted. */
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bool mispredicted()
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{
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return readPredPC() != readNextPC() ||
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readPredNPC() != readNextNPC() ||
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readPredMicroPC() != readNextMicroPC();
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}
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//
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// Instruction types. Forward checks to StaticInst object.
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//
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bool isNop() const { return staticInst->isNop(); }
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isStoreConditional() const
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{ return staticInst->isStoreConditional(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
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bool isCopy() const { return staticInst->isCopy(); }
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bool isInteger() const { return staticInst->isInteger(); }
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bool isFloating() const { return staticInst->isFloating(); }
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bool isControl() const { return staticInst->isControl(); }
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bool isCall() const { return staticInst->isCall(); }
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bool isReturn() const { return staticInst->isReturn(); }
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bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool isSerializeBefore() const
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{ return staticInst->isSerializeBefore() || status[SerializeBefore]; }
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bool isSerializeAfter() const
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{ return staticInst->isSerializeAfter() || status[SerializeAfter]; }
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bool isMemBarrier() const { return staticInst->isMemBarrier(); }
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bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
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bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
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bool isQuiesce() const { return staticInst->isQuiesce(); }
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bool isIprAccess() const { return staticInst->isIprAccess(); }
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bool isUnverifiable() const { return staticInst->isUnverifiable(); }
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bool isSyscall() const { return staticInst->isSyscall(); }
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bool isMacroop() const { return staticInst->isMacroop(); }
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bool isMicroop() const { return staticInst->isMicroop(); }
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bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
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bool isLastMicroop() const { return staticInst->isLastMicroop(); }
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bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
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bool isMicroBranch() const { return staticInst->isMicroBranch(); }
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/** Temporarily sets this instruction as a serialize before instruction. */
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void setSerializeBefore() { status.set(SerializeBefore); }
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/** Clears the serializeBefore part of this instruction. */
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void clearSerializeBefore() { status.reset(SerializeBefore); }
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/** Checks if this serializeBefore is only temporarily set. */
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bool isTempSerializeBefore() { return status[SerializeBefore]; }
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/** Temporarily sets this instruction as a serialize after instruction. */
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void setSerializeAfter() { status.set(SerializeAfter); }
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/** Clears the serializeAfter part of this instruction.*/
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void clearSerializeAfter() { status.reset(SerializeAfter); }
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/** Checks if this serializeAfter is only temporarily set. */
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bool isTempSerializeAfter() { return status[SerializeAfter]; }
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/** Sets the serialization part of this instruction as handled. */
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void setSerializeHandled() { status.set(SerializeHandled); }
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/** Checks if the serialization part of this instruction has been
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* handled. This does not apply to the temporary serializing
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* state; it only applies to this instruction's own permanent
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* serializing state.
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*/
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bool isSerializeHandled() { return status[SerializeHandled]; }
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/** Returns the opclass of this instruction. */
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OpClass opClass() const { return staticInst->opClass(); }
|
|
|
|
/** Returns the branch target address. */
|
|
Addr branchTarget() const { return staticInst->branchTarget(PC); }
|
|
|
|
/** Returns the number of source registers. */
|
|
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
|
|
|
|
/** Returns the number of destination registers. */
|
|
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
|
|
|
|
// the following are used to track physical register usage
|
|
// for machines with separate int & FP reg files
|
|
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
|
|
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
|
|
|
/** Returns the logical register index of the i'th destination register. */
|
|
RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
|
|
|
|
/** Returns the logical register index of the i'th source register. */
|
|
RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
|
|
|
|
/** Returns the result of an integer instruction. */
|
|
uint64_t readIntResult() { return instResult.integer; }
|
|
|
|
/** Returns the result of a floating point instruction. */
|
|
float readFloatResult() { return (float)instResult.dbl; }
|
|
|
|
/** Returns the result of a floating point (double) instruction. */
|
|
double readDoubleResult() { return instResult.dbl; }
|
|
|
|
/** Records an integer register being set to a value. */
|
|
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
|
{
|
|
if (recordResult)
|
|
instResult.integer = val;
|
|
}
|
|
|
|
/** Records an fp register being set to a value. */
|
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
|
int width)
|
|
{
|
|
if (recordResult) {
|
|
if (width == 32)
|
|
instResult.dbl = (double)val;
|
|
else if (width == 64)
|
|
instResult.dbl = val;
|
|
else
|
|
panic("Unsupported width!");
|
|
}
|
|
}
|
|
|
|
/** Records an fp register being set to a value. */
|
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
|
{
|
|
if (recordResult)
|
|
instResult.dbl = (double)val;
|
|
}
|
|
|
|
/** Records an fp register being set to an integer value. */
|
|
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
|
|
int width)
|
|
{
|
|
if (recordResult)
|
|
instResult.integer = val;
|
|
}
|
|
|
|
/** Records an fp register being set to an integer value. */
|
|
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
|
|
{
|
|
if (recordResult)
|
|
instResult.integer = val;
|
|
}
|
|
|
|
/** Records that one of the source registers is ready. */
|
|
void markSrcRegReady();
|
|
|
|
/** Marks a specific register as ready. */
|
|
void markSrcRegReady(RegIndex src_idx);
|
|
|
|
/** Returns if a source register is ready. */
|
|
bool isReadySrcRegIdx(int idx) const
|
|
{
|
|
return this->_readySrcRegIdx[idx];
|
|
}
|
|
|
|
/** Sets this instruction as completed. */
|
|
void setCompleted() { status.set(Completed); }
|
|
|
|
/** Returns whether or not this instruction is completed. */
|
|
bool isCompleted() const { return status[Completed]; }
|
|
|
|
/** Marks the result as ready. */
|
|
void setResultReady() { status.set(ResultReady); }
|
|
|
|
/** Returns whether or not the result is ready. */
|
|
bool isResultReady() const { return status[ResultReady]; }
|
|
|
|
/** Sets this instruction as ready to issue. */
|
|
void setCanIssue() { status.set(CanIssue); }
|
|
|
|
/** Returns whether or not this instruction is ready to issue. */
|
|
bool readyToIssue() const { return status[CanIssue]; }
|
|
|
|
/** Clears this instruction being able to issue. */
|
|
void clearCanIssue() { status.reset(CanIssue); }
|
|
|
|
/** Sets this instruction as issued from the IQ. */
|
|
void setIssued() { status.set(Issued); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isIssued() const { return status[Issued]; }
|
|
|
|
/** Clears this instruction as being issued. */
|
|
void clearIssued() { status.reset(Issued); }
|
|
|
|
/** Sets this instruction as executed. */
|
|
void setExecuted() { status.set(Executed); }
|
|
|
|
/** Returns whether or not this instruction has executed. */
|
|
bool isExecuted() const { return status[Executed]; }
|
|
|
|
/** Sets this instruction as ready to commit. */
|
|
void setCanCommit() { status.set(CanCommit); }
|
|
|
|
/** Clears this instruction as being ready to commit. */
|
|
void clearCanCommit() { status.reset(CanCommit); }
|
|
|
|
/** Returns whether or not this instruction is ready to commit. */
|
|
bool readyToCommit() const { return status[CanCommit]; }
|
|
|
|
void setAtCommit() { status.set(AtCommit); }
|
|
|
|
bool isAtCommit() { return status[AtCommit]; }
|
|
|
|
/** Sets this instruction as committed. */
|
|
void setCommitted() { status.set(Committed); }
|
|
|
|
/** Returns whether or not this instruction is committed. */
|
|
bool isCommitted() const { return status[Committed]; }
|
|
|
|
/** Sets this instruction as squashed. */
|
|
void setSquashed() { status.set(Squashed); }
|
|
|
|
/** Returns whether or not this instruction is squashed. */
|
|
bool isSquashed() const { return status[Squashed]; }
|
|
|
|
//Instruction Queue Entry
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void setInIQ() { status.set(IqEntry); }
|
|
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void clearInIQ() { status.reset(IqEntry); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isInIQ() const { return status[IqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the IQ. */
|
|
void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the IQ. */
|
|
bool isSquashedInIQ() const { return status[SquashedInIQ]; }
|
|
|
|
|
|
//Load / Store Queue Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void setInLSQ() { status.set(LsqEntry); }
|
|
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void removeInLSQ() { status.reset(LsqEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the LSQ. */
|
|
bool isInLSQ() const { return status[LsqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the LSQ. */
|
|
void setSquashedInLSQ() { status.set(SquashedInLSQ);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the LSQ. */
|
|
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
|
|
|
|
|
|
//Reorder Buffer Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void setInROB() { status.set(RobEntry); }
|
|
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void clearInROB() { status.reset(RobEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the ROB. */
|
|
bool isInROB() const { return status[RobEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the ROB. */
|
|
void setSquashedInROB() { status.set(SquashedInROB); }
|
|
|
|
/** Returns whether or not this instruction is squashed in the ROB. */
|
|
bool isSquashedInROB() const { return status[SquashedInROB]; }
|
|
|
|
/** Read the PC of this instruction. */
|
|
const Addr readPC() const { return PC; }
|
|
|
|
/**Read the micro PC of this instruction. */
|
|
const Addr readMicroPC() const { return microPC; }
|
|
|
|
/** Set the next PC of this instruction (its actual target). */
|
|
void setNextPC(Addr val)
|
|
{
|
|
nextPC = val;
|
|
}
|
|
|
|
/** Set the next NPC of this instruction (the target in Mips or Sparc).*/
|
|
void setNextNPC(Addr val)
|
|
{
|
|
#if ISA_HAS_DELAY_SLOT
|
|
nextNPC = val;
|
|
#endif
|
|
}
|
|
|
|
void setNextMicroPC(Addr val)
|
|
{
|
|
nextMicroPC = val;
|
|
}
|
|
|
|
/** Sets the ASID. */
|
|
void setASID(short addr_space_id) { asid = addr_space_id; }
|
|
|
|
/** Sets the thread id. */
|
|
void setTid(unsigned tid) { threadNumber = tid; }
|
|
|
|
/** Sets the pointer to the thread state. */
|
|
void setThreadState(ImplState *state) { thread = state; }
|
|
|
|
/** Returns the thread context. */
|
|
ThreadContext *tcBase() { return thread->getTC(); }
|
|
|
|
private:
|
|
/** Instruction effective address.
|
|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
Addr instEffAddr;
|
|
|
|
/** Whether or not the effective address calculation is completed.
|
|
* @todo: Consider if this is necessary or not.
|
|
*/
|
|
bool eaCalcDone;
|
|
|
|
/** Is this instruction's memory access uncacheable. */
|
|
bool isUncacheable;
|
|
|
|
/** Has this instruction generated a memory request. */
|
|
bool reqMade;
|
|
|
|
public:
|
|
/** Sets the effective address. */
|
|
void setEA(Addr &ea) { instEffAddr = ea; eaCalcDone = true; }
|
|
|
|
/** Returns the effective address. */
|
|
const Addr &getEA() const { return instEffAddr; }
|
|
|
|
/** Returns whether or not the eff. addr. calculation has been completed. */
|
|
bool doneEACalc() { return eaCalcDone; }
|
|
|
|
/** Returns whether or not the eff. addr. source registers are ready. */
|
|
bool eaSrcsReady();
|
|
|
|
/** Whether or not the memory operation is done. */
|
|
bool memOpDone;
|
|
|
|
/** Is this instruction's memory access uncacheable. */
|
|
bool uncacheable() { return isUncacheable; }
|
|
|
|
/** Has this instruction generated a memory request. */
|
|
bool hasRequest() { return reqMade; }
|
|
|
|
public:
|
|
/** Load queue index. */
|
|
int16_t lqIdx;
|
|
|
|
/** Store queue index. */
|
|
int16_t sqIdx;
|
|
|
|
/** Iterator pointing to this BaseDynInst in the list of all insts. */
|
|
ListIt instListIt;
|
|
|
|
/** Returns iterator to this instruction in the list of all insts. */
|
|
ListIt &getInstListIt() { return instListIt; }
|
|
|
|
/** Sets iterator for this instruction in the list of all insts. */
|
|
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
|
|
|
public:
|
|
/** Returns the number of consecutive store conditional failures. */
|
|
unsigned readStCondFailures()
|
|
{ return thread->storeCondFailures; }
|
|
|
|
/** Sets the number of consecutive store conditional failures. */
|
|
void setStCondFailures(unsigned sc_failures)
|
|
{ thread->storeCondFailures = sc_failures; }
|
|
};
|
|
|
|
template<class Impl>
|
|
template<class T>
|
|
inline Fault
|
|
BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
|
|
{
|
|
reqMade = true;
|
|
Request *req = new Request();
|
|
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
|
|
req->setThreadContext(thread->readCpuId(), threadNumber);
|
|
|
|
fault = cpu->translateDataReadReq(req, thread);
|
|
|
|
if (req->isUncacheable())
|
|
isUncacheable = true;
|
|
|
|
if (fault == NoFault) {
|
|
effAddr = req->getVaddr();
|
|
effAddrValid = true;
|
|
physEffAddr = req->getPaddr();
|
|
memReqFlags = req->getFlags();
|
|
|
|
#if 0
|
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
|
fault = TheISA::genMachineCheckFault();
|
|
data = (T)-1;
|
|
this->setExecuted();
|
|
} else {
|
|
fault = cpu->read(req, data, lqIdx);
|
|
}
|
|
#else
|
|
fault = cpu->read(req, data, lqIdx);
|
|
#endif
|
|
} else {
|
|
// Return a fixed value to keep simulation deterministic even
|
|
// along misspeculated paths.
|
|
data = (T)-1;
|
|
|
|
// Commit will have to clean up whatever happened. Set this
|
|
// instruction as executed.
|
|
this->setExecuted();
|
|
delete req;
|
|
}
|
|
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
traceData->setData(data);
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
template<class Impl>
|
|
template<class T>
|
|
inline Fault
|
|
BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
traceData->setData(data);
|
|
}
|
|
|
|
reqMade = true;
|
|
Request *req = new Request();
|
|
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
|
|
req->setThreadContext(thread->readCpuId(), threadNumber);
|
|
|
|
fault = cpu->translateDataWriteReq(req, thread);
|
|
|
|
if (req->isUncacheable())
|
|
isUncacheable = true;
|
|
|
|
if (fault == NoFault) {
|
|
effAddr = req->getVaddr();
|
|
effAddrValid = true;
|
|
physEffAddr = req->getPaddr();
|
|
memReqFlags = req->getFlags();
|
|
|
|
if (req->isCondSwap()) {
|
|
assert(res);
|
|
req->setExtraData(*res);
|
|
}
|
|
#if 0
|
|
if (cpu->system->memctrl->badaddr(physEffAddr)) {
|
|
fault = TheISA::genMachineCheckFault();
|
|
} else {
|
|
fault = cpu->write(req, data, sqIdx);
|
|
}
|
|
#else
|
|
fault = cpu->write(req, data, sqIdx);
|
|
#endif
|
|
} else {
|
|
delete req;
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
#endif // __CPU_BASE_DYN_INST_HH__
|