e2507407b1
Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
111 lines
3.8 KiB
C++
111 lines
3.8 KiB
C++
/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __SIM_TLB_HH__
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#define __SIM_TLB_HH__
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#include "base/misc.hh"
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#include "mem/request.hh"
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#include "sim/fault_fwd.hh"
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#include "sim/sim_object.hh"
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class ThreadContext;
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class Packet;
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class Port;
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class BaseTLB : public SimObject
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{
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protected:
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BaseTLB(const Params *p)
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: SimObject(p)
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{}
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public:
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enum Mode { Read, Write, Execute };
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public:
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virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
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/** Get any port that the TLB or hardware table walker needs.
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* This is used for migrating port connections during a takeOverFrom()
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* call. */
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virtual Port* getPort() { return NULL; }
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class Translation
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{
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public:
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virtual ~Translation()
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{}
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/**
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* Signal that the translation has been delayed due to a hw page table
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* walk.
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*/
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virtual void markDelayed() = 0;
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/*
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* The memory for this object may be dynamically allocated, and it may
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* be responsible for cleaning itself up which will happen in this
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* function. Once it's called, the object is no longer valid.
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*/
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virtual void finish(Fault fault, RequestPtr req, ThreadContext *tc,
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Mode mode) = 0;
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};
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};
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class GenericTLB : public BaseTLB
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{
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protected:
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GenericTLB(const Params *p)
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: BaseTLB(p)
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{}
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public:
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void demapPage(Addr vaddr, uint64_t asn);
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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void translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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};
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#endif // __ARCH_SPARC_TLB_HH__
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