394 lines
16 KiB
C++
394 lines
16 KiB
C++
/*
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* Copyright (c) 2009 Princeton University
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* Copyright (c) 2009 The Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Hangsheng Wang (Orion 1.0, Princeton)
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* Xinping Zhu (Orion 1.0, Princeton)
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* Xuning Chen (Orion 1.0, Princeton)
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* Bin Li (Orion 2.0, Princeton)
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* Kambiz Samadi (Orion 2.0, UC San Diego)
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*/
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#include <cassert>
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#include <iostream>
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#include "mem/ruby/network/orion/Crossbar/Crossbar.hh"
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#include "mem/ruby/network/orion/Crossbar/MatrixCrossbar.hh"
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#include "mem/ruby/network/orion/Crossbar/MultreeCrossbar.hh"
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#include "mem/ruby/network/orion/OrionConfig.hh"
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#include "mem/ruby/network/orion/TechParameter.hh"
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using namespace std;
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Crossbar::Crossbar(
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CrossbarModel xbar_model_,
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const string& conn_type_str_,
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const string& trans_type_str_,
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uint32_t num_in_,
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uint32_t num_out_,
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uint32_t data_width_,
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uint32_t num_in_seg_,
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uint32_t num_out_seg_,
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uint32_t degree_,
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const TechParameter* tech_param_ptr_
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)
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{
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m_xbar_model = xbar_model_;
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if (m_xbar_model != NO_MODEL)
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{
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assert((num_in_ == num_in_) && (num_in_ != 0));
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assert((num_out_ == num_out_) && (num_out_ != 0));
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assert((data_width_ == data_width_) && (data_width_ != 0));
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assert(num_in_seg_ == num_in_seg_);
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assert(num_out_seg_ == num_out_seg_);
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set_conn_type(conn_type_str_);
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set_trans_type(trans_type_str_);
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m_num_in = num_in_;
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m_num_out = num_out_;
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m_num_in_seg = num_in_seg_;
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m_num_out_seg = num_out_seg_;
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m_data_width = data_width_;
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m_degree = degree_;
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m_tech_param_ptr = tech_param_ptr_;
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}
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else
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{
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cerr << "ERROR at " << __FILE__ << " " << __LINE__ << endl;
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}
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}
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Crossbar::~Crossbar()
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{}
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double Crossbar::get_static_power() const
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{
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double vdd = m_tech_param_ptr->get_vdd();
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double SCALE_S = m_tech_param_ptr->get_SCALE_S();
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return (m_i_static*vdd*SCALE_S);
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}
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void Crossbar::print_all() const
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{
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cout << "Crossbar" << endl;
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cout << "\t" << "Traversal = " << get_dynamic_energy(false) << endl;
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cout << "\t" << "Static power = " << get_static_power() << endl;
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return;
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}
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void Crossbar::set_conn_type(const string& conn_type_str_)
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{
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if (conn_type_str_ == string("TRANS_GATE"))
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{
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m_conn_type = TRANS_GATE;
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}
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else if (conn_type_str_ == string("TRISTATE_GATE"))
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{
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m_conn_type = TRISTATE_GATE;
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}
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else
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{
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cerr << "Invalid connect type: '" << conn_type_str_ << "'. Use TRANS_GATE as default." << endl;
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m_conn_type = TRANS_GATE;
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}
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return;
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}
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void Crossbar::set_trans_type(const string& trans_type_str_)
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{
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if (trans_type_str_ == string("NP_GATE"))
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{
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m_trans_type = NP_GATE;
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}
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else if (trans_type_str_ == string("N_GATE"))
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{
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m_trans_type = N_GATE;
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}
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else
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{
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cerr << "Invalid trans type: '" << trans_type_str_ << "'. Use N_GATE as default." << endl;
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m_trans_type = N_GATE;
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}
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}
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double Crossbar::calc_in_cap()
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{
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double total_cap = 0;
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// part 1: wire cap
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total_cap += m_cap_in_wire;
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double trans_cap = 0;
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// part 2: drain cap of transmission gate or gate cap of tri-state gate
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if (m_conn_type == TRANS_GATE)
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{
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//FIXME: resizing strategy
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double Wmemcellr = m_tech_param_ptr->get_Wmemcellr();
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double nsize = Wmemcellr;
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double psize = nsize*Wdecinvp/Wdecinvn;
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trans_cap = m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1);
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if (m_trans_type == NP_GATE)
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{
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trans_cap += m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1);
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}
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}
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else if (m_conn_type == TRISTATE_GATE)
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{
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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trans_cap = m_tech_param_ptr->calc_gatecap(Woutdrvnandn+Woutdrvnandp, 0)
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+ m_tech_param_ptr->calc_gatecap(Woutdrvnorn+Woutdrvnorp, 0);
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}
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total_cap += trans_cap*m_num_out;
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// segmented crossbar
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if (m_num_in_seg > 1)
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{
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total_cap *= (m_num_in_seg+1)/(m_num_in_seg*2);
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// input capacitance of tri-state buffer
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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total_cap += (m_num_in_seg+2)*(m_num_in_seg-1)/(m_num_in_seg*2)*(m_tech_param_ptr->calc_gatecap(Woutdrvnandn+Woutdrvnandp, 0)+m_tech_param_ptr->calc_gatecap(Woutdrvnorn+Woutdrvnorp, 0));
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// output capacitance of tri-state buffer
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double Woutdrivern = m_tech_param_ptr->get_Woutdrivern();
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double Woutdriverp = m_tech_param_ptr->get_Woutdriverp();
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total_cap += (m_num_in_seg-1)/2*(m_tech_param_ptr->calc_draincap(Woutdrivern, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Woutdriverp, TechParameter::PCH, 1));
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}
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// part 3: input driver
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//FIXME: how to specify timing
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double period = m_tech_param_ptr->get_period();
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double psize = m_tech_param_ptr->calc_driver_psize(total_cap, period/3.0);
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double nsize = psize*Wdecinvn/Wdecinvp;
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total_cap += m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1)+m_tech_param_ptr->calc_gatecap(nsize+psize, 0);
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return total_cap/2.0;
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}
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double Crossbar::calc_out_cap(uint32_t num_in_)
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{
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double total_cap = 0;
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// part 1: wire cap
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total_cap += m_cap_out_wire;
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double trans_cap = 0;
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// part 2: drain cap of transmission gate or tri-state gate
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if (m_conn_type == TRANS_GATE)
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{
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// FIXME: resizing strategy
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double Wmemcellr = m_tech_param_ptr->get_Wmemcellr();
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double nsize = Wmemcellr;
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double psize = nsize*Wdecinvp/Wdecinvn;
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trans_cap = m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1);
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if (m_trans_type == NP_GATE)
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{
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trans_cap += m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1);
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}
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}
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else if (m_conn_type == TRISTATE_GATE)
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{
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double Woutdrivern = m_tech_param_ptr->get_Woutdrivern();
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double Woutdriverp = m_tech_param_ptr->get_Woutdriverp();
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trans_cap = m_tech_param_ptr->calc_draincap(Woutdrivern, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Woutdriverp, TechParameter::PCH, 1);
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}
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total_cap += trans_cap*num_in_;
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// segmented crossbar
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if (m_num_out_seg > 1)
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{
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total_cap *= (m_num_out_seg+1)/(m_num_out_seg*2);
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// input capacitance of tri-state buffer
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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total_cap += (m_num_out_seg+2)*(m_num_out_seg-1)/(m_num_out_seg*2)*(m_tech_param_ptr->calc_gatecap(Woutdrvnandn+Woutdrvnandp, 0)+m_tech_param_ptr->calc_gatecap(Woutdrvnorn+Woutdrvnorp, 0));
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// output capacitance of tri-state buffer
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double Woutdrivern = m_tech_param_ptr->get_Woutdrivern();
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double Woutdriverp = m_tech_param_ptr->get_Woutdriverp();
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total_cap += (m_num_out_seg-1)/2*(m_tech_param_ptr->calc_draincap(Woutdrivern, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Woutdriverp, TechParameter::PCH, 1));
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}
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// part 3: output driver
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double Woutdrivern = m_tech_param_ptr->get_Woutdrivern();
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double Woutdriverp = m_tech_param_ptr->get_Woutdriverp();
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total_cap += m_tech_param_ptr->calc_draincap(Woutdrivern, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Woutdriverp, TechParameter::PCH, 1)+m_tech_param_ptr->calc_gatecap(Woutdrivern+Woutdriverp, 0);
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return total_cap/2.0;
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}
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double Crossbar::calc_int_cap()
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{
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double total_cap = 0;
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if (m_conn_type == TRANS_GATE)
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{
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// part 1: drain cap of transmission gate
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//FIXME: Wmemcellr and resize
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double Wmemcellr = m_tech_param_ptr->get_Wmemcellr();
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double nsize = Wmemcellr;
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double trans_cap = m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1);
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if (m_trans_type == NP_GATE)
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{
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double psize = nsize*Wdecinvp/Wdecinvn;
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trans_cap += m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1);
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}
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total_cap += trans_cap*(m_degree+1);
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}
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else if (m_conn_type == TRISTATE_GATE)
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{
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// part 1: drain cap of tri-state gate
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double Woutdrivern = m_tech_param_ptr->get_Woutdrivern();
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double Woutdriverp = m_tech_param_ptr->get_Woutdriverp();
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double trans_cap = (m_tech_param_ptr->calc_draincap(Woutdrivern, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Woutdriverp, TechParameter::PCH, 1))*m_degree;
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// part 2: gate cap of tri-state gate
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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trans_cap += m_tech_param_ptr->calc_gatecap(Woutdrvnandn+Woutdrvnandp, 0)+m_tech_param_ptr->calc_gatecap(Woutdrvnorn+Woutdrvnorp, 0);
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total_cap += trans_cap;
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}
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return total_cap/2.0;
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}
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double Crossbar::calc_ctr_cap(double cap_wire_, bool prev_ctr_, bool next_ctr_)
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{
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double total_cap = 0;
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// part 1: wire cap
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total_cap += cap_wire_;
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double trans_cap = 0;
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// part 2: gate cap of transmission gate or tri-state gate
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if (m_conn_type == TRANS_GATE)
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{
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//FIXME Wmemcellr and resize
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double Wmemcellr = m_tech_param_ptr->get_Wmemcellr();
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double nsize = Wmemcellr;
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double trans_cap = m_tech_param_ptr->calc_gatecap(nsize, 0);
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if (m_trans_type == NP_GATE)
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{
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double psize = nsize*Wdecinvp/Wdecinvn;
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trans_cap += m_tech_param_ptr->calc_gatecap(psize, 0);
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}
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}
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else if (m_conn_type == TRISTATE_GATE)
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{
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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trans_cap = m_tech_param_ptr->calc_gatecap(Woutdrvnandn+Woutdrvnandp, 0)
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+ m_tech_param_ptr->calc_gatecap(Woutdrvnorn+Woutdrvnorp, 0);
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}
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total_cap += trans_cap*m_data_width;
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// part 3: inverter
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if (!((m_conn_type == TRANS_GATE) && (m_trans_type == N_GATE) && (!prev_ctr_)))
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{
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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total_cap += m_tech_param_ptr->calc_draincap(Wdecinvn, TechParameter::NCH, 1)+m_tech_param_ptr->calc_draincap(Wdecinvp, TechParameter::PCH, 1)
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+ m_tech_param_ptr->calc_gatecap(Wdecinvn+Wdecinvp, 0);
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}
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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// part 4: drain cap of previous level control signal
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if (prev_ctr_)
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{
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// FIXME: need actual size, use decoder data for now
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total_cap += m_degree*m_tech_param_ptr->calc_draincap(WdecNORn, TechParameter::NCH, 1)
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+m_tech_param_ptr->calc_draincap(WdecNORp, TechParameter::PCH, m_degree);
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}
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// part 5: gate cap of next level control signal
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if (next_ctr_)
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{
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// FIXME: need actual size, use decoder data for now
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total_cap += m_tech_param_ptr->calc_gatecap(WdecNORn+WdecNORp, m_degree*40+20);
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}
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return total_cap;
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}
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Crossbar* Crossbar::create_crossbar(
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const string& xbar_model_str_,
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uint32_t num_in_,
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uint32_t num_out_,
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uint32_t data_width_,
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const OrionConfig* orion_cfg_ptr_
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)
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{
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if (xbar_model_str_ == string("MATRIX_CROSSBAR"))
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{
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const string& conn_type_str = orion_cfg_ptr_->get<string>("CROSSBAR_CONNECT_TYPE");
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const string& trans_type_str = orion_cfg_ptr_->get<string>("CROSSBAR_TRANS_GATE_TYPE");
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uint32_t num_in_seg = orion_cfg_ptr_->get<uint32_t>("CROSSBAR_NUM_IN_SEG");
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uint32_t num_out_seg = orion_cfg_ptr_->get<uint32_t>("CROSSBAR_NUM_OUT_SEG");
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double len_in_wire = orion_cfg_ptr_->get<double>("CROSSBAR_LEN_IN_WIRE");
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double len_out_wire = orion_cfg_ptr_->get<double>("CROSSBAR_LEN_OUT_WIRE");
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const TechParameter* tech_param_ptr = orion_cfg_ptr_->get_tech_param_ptr();
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return new MatrixCrossbar(conn_type_str, trans_type_str,
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num_in_, num_out_, data_width_, num_in_seg, num_out_seg,
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len_in_wire, len_out_wire, tech_param_ptr);
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}
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else if (xbar_model_str_ == string("MULTREE_CROSSBAR"))
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{
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const string& conn_type_str = orion_cfg_ptr_->get<string>("CROSSBAR_CONNECT_TYPE");
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const string& trans_type_str = orion_cfg_ptr_->get<string>("CROSSBAR_TRANS_GATE_TYPE");
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uint32_t degree = orion_cfg_ptr_->get<uint32_t>("CROSSBAR_MUX_DEGREE");
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const TechParameter* tech_param_ptr = orion_cfg_ptr_->get_tech_param_ptr();
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return new MultreeCrossbar(conn_type_str, trans_type_str,
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num_in_, num_out_, data_width_, degree, tech_param_ptr);
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}
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else
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{
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cerr << "WARNING: No Crossbar model" << endl;
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return (Crossbar*)NULL;
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}
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}
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