201 lines
7.1 KiB
C++
201 lines
7.1 KiB
C++
/*
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* Copyright (c) 2009 Princeton University
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* Copyright (c) 2009 The Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Hangsheng Wang (Orion 1.0, Princeton)
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* Xinping Zhu (Orion 1.0, Princeton)
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* Xuning Chen (Orion 1.0, Princeton)
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* Bin Li (Orion 2.0, Princeton)
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* Kambiz Samadi (Orion 2.0, UC San Diego)
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*/
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#include "base/misc.hh"
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#include "mem/ruby/network/orion/Buffer/BitlineUnit.hh"
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#include "mem/ruby/network/orion/Buffer/SRAM.hh"
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#include "mem/ruby/network/orion/TechParameter.hh"
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BitlineUnit::BitlineUnit(
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const string bl_model_str_,
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const SRAM* sram_ptr_,
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const TechParameter* tech_param_ptr_
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)
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{
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if (bl_model_str_ == "RW_BITLINE")
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{
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m_bl_model = RW_BITLINE;
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}
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else if (bl_model_str_ == "WO_BITLINE")
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{
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m_bl_model = WO_BITLINE;
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}
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else
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{
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m_bl_model = NO_MODEL;
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}
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if (m_bl_model != NO_MODEL)
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{
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m_sram_ptr = sram_ptr_;
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m_tech_param_ptr = tech_param_ptr_;
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init();
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}
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}
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BitlineUnit::~BitlineUnit()
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{}
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void BitlineUnit::init()
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{
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uint32_t num_port = m_sram_ptr->get_num_port();
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uint32_t num_data_end = m_sram_ptr->get_num_data_end();
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double bl_cmetal;
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if ((num_port > 1) || (num_data_end == 2))
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{
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bl_cmetal = m_tech_param_ptr->get_CC3M2metal();
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}
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else
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{
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bl_cmetal = m_tech_param_ptr->get_CM2metal();
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}
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uint32_t num_row = m_sram_ptr->get_num_row();
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double RegCellHeight = m_tech_param_ptr->get_RegCellHeight();
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double WordlineSpacing = m_tech_param_ptr->get_WordlineSpacing();
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m_bl_len = num_row*(RegCellHeight + num_port*WordlineSpacing);
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m_bl_wire_cap = m_bl_len * bl_cmetal;
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double e_factor = m_tech_param_ptr->get_EnergyFactor();
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double sense_e_factor = m_tech_param_ptr->get_SenseEnergyFactor();
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switch(m_bl_model)
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{
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case RW_BITLINE:
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if (num_data_end == 2)
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{
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m_e_col_sel = calc_col_select_cap() * e_factor;
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m_e_col_read = calc_col_read_cap() * sense_e_factor;
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}
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else
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{
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m_e_col_sel = 0;
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m_e_col_read = calc_col_read_cap() * e_factor;
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}
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m_e_col_write = calc_col_write_cap() * e_factor;
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m_i_static = calc_i_static();
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break;
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case WO_BITLINE:
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m_e_col_sel = m_e_col_read = 0;
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m_e_col_write = calc_col_write_cap() * e_factor;
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//FIXME - no static power?
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break;
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default:
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fatal("Error in BITLINE model.\n");
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}
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return;
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}
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double BitlineUnit::calc_col_select_cap()
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{
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double Wbitmuxn = m_tech_param_ptr->get_Wbitmuxn();
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return m_tech_param_ptr->calc_gatecap(Wbitmuxn, 1);
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}
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double BitlineUnit::calc_col_read_cap()
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{
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double total_cap = 0;
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// part 1: drain cap of precharge tx's
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//total_cap = m_num_bl_pre * Util::calc_draincap(m_pre_size, Util::PCH, 1);
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// part 2: drain cap of pass tx's
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double Wmemcellr = m_tech_param_ptr->get_Wmemcellr();
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uint32_t num_row = m_sram_ptr->get_num_row();
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total_cap = num_row * m_tech_param_ptr->calc_draincap(Wmemcellr, TechParameter::NCH, 1);
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// part 3: metal cap
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total_cap += m_bl_wire_cap;
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m_pre_unit_load = total_cap;
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// part 4: bitline inverter
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uint32_t num_data_end = m_sram_ptr->get_num_data_end();
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if (num_data_end == 1)
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{
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// FIXME: magic numbers
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double MSCALE = m_tech_param_ptr->get_MSCALE();
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total_cap += m_tech_param_ptr->calc_gatecap(MSCALE * (29.9 + 7.8), 0) + m_tech_param_ptr->calc_gatecap(MSCALE * (47.0 + 12.0), 0);
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}
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// part 5: gate cap of sense amplifier or output driver
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bool is_outdrv = m_sram_ptr->get_is_outdrv();
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if (num_data_end == 2)
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{ // sense amplifier
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double WsenseQ1to4 = m_tech_param_ptr->get_WsenseQ1to4();
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total_cap += 2 * m_tech_param_ptr->calc_gatecap(WsenseQ1to4, 10);
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}
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else if (is_outdrv)
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{
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double Woutdrvnandn = m_tech_param_ptr->get_Woutdrvnandn();
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double Woutdrvnandp = m_tech_param_ptr->get_Woutdrvnandp();
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double Woutdrvnorn = m_tech_param_ptr->get_Woutdrvnorn();
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double Woutdrvnorp = m_tech_param_ptr->get_Woutdrvnorp();
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total_cap += m_tech_param_ptr->calc_gatecap(Woutdrvnandn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnandp, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorn, 1) + m_tech_param_ptr->calc_gatecap(Woutdrvnorp, 1);
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}
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return total_cap;
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}
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double BitlineUnit::calc_col_write_cap()
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{
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double total_cap, psize, nsize;
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// part 1: line cap, including drain cap of pass tx's and metal cap
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uint32_t num_row = m_sram_ptr->get_num_row();
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double Wmemcellw = m_tech_param_ptr->get_Wmemcellw();
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total_cap = num_row * m_tech_param_ptr->calc_draincap(Wmemcellw, TechParameter::NCH, 1) + m_bl_wire_cap;
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// part 2: write driver
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double period = m_tech_param_ptr->get_period();
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psize = m_tech_param_ptr->calc_driver_psize(total_cap, period / 8.0);
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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nsize = psize * Wdecinvn / Wdecinvp;
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total_cap += m_tech_param_ptr->calc_draincap(psize, TechParameter::PCH, 1) + m_tech_param_ptr->calc_draincap(nsize, TechParameter::NCH, 1) + m_tech_param_ptr->calc_gatecap(psize + nsize, 1);
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return total_cap;
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}
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double BitlineUnit::calc_i_static()
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{
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double NMOS_TAB_0 = m_tech_param_ptr->get_NMOS_TAB(0);
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double PMOS_TAB_0 = m_tech_param_ptr->get_PMOS_TAB(0);
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return (2*(Wdecinvn*NMOS_TAB_0+Wdecinvp*PMOS_TAB_0));
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}
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