239 lines
7.9 KiB
C++
239 lines
7.9 KiB
C++
/*
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* Copyright (c) 2009 Princeton University
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* Copyright (c) 2009 The Regents of the University of California
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Hangsheng Wang (Orion 1.0, Princeton)
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* Xinping Zhu (Orion 1.0, Princeton)
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* Xuning Chen (Orion 1.0, Princeton)
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* Bin Li (Orion 2.0, Princeton)
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* Kambiz Samadi (Orion 2.0, UC San Diego)
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*/
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#include <cmath>
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#include <iostream>
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#include "mem/ruby/network/orion/Allocator/RRArbiter.hh"
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#include "mem/ruby/network/orion/FlipFlop.hh"
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#include "mem/ruby/network/orion/TechParameter.hh"
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using namespace std;
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RRArbiter::RRArbiter(
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const string& ff_model_str_,
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uint32_t req_width_,
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double len_in_wire_,
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const TechParameter* tech_param_ptr_
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) : Arbiter(RR_ARBITER, req_width_, len_in_wire_, tech_param_ptr_)
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{
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init(ff_model_str_);
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}
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RRArbiter::~RRArbiter()
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{
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delete m_ff_ptr;
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}
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double RRArbiter::calc_dynamic_energy(double num_req_, bool is_max_) const
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{
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if (num_req_ > m_req_width)
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{
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cerr << "WARNING: (num_req_ > m_req_width). Set num_req_ = m_req_width" << endl;
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num_req_ = m_req_width;
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}
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double num_grant;
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if (num_req_ >= 1) num_grant = 1;
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else if (num_req_) num_grant = 1.0 / ceil(1.0/num_req_);
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else num_grant = 0;
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double e_atomic;
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double e_arb = 0;
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e_atomic = m_e_chg_req*num_req_;
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e_arb += e_atomic;
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e_atomic = m_e_chg_grant*num_grant;
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e_arb += e_atomic;
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// assume carry signal propagates half length in average case */
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// carry does not propagate in maximum case, i.e. all carrys go down */
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e_atomic = m_e_chg_carry*m_req_width*(is_max_? 1:0.5)*num_grant;
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e_arb += e_atomic;
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e_atomic = m_e_chg_carry_in*(m_req_width*(is_max_? 1:0.5)-1)*num_grant;
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e_arb += e_atomic;
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// priority register
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e_atomic = m_ff_ptr->get_e_switch()*2*num_grant;
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e_arb += e_atomic;
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e_atomic = m_ff_ptr->get_e_keep_0()*(m_req_width-2*num_grant);
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e_arb += e_atomic;
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e_atomic = m_ff_ptr->get_e_clock()*m_req_width;
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e_arb += e_atomic;
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return e_arb;
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}
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void RRArbiter::init(const string& ff_model_str_)
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{
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double e_factor = m_tech_param_ptr->get_EnergyFactor();
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m_e_chg_req = calc_req_cap()/2*e_factor;
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// two grant signals switch together, so no 1/2
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m_e_chg_grant = calc_grant_cap()*e_factor;
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m_e_chg_carry = calc_carry_cap()/2*e_factor;
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m_e_chg_carry_in = calc_carry_in_cap()/2*e_factor;
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double ff_load = calc_pri_cap();
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m_ff_ptr = new FlipFlop(ff_model_str_, ff_load, m_tech_param_ptr);
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m_i_static = calc_i_static();
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return;
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}
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// switch cap of request signal (round robin arbiter)
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double RRArbiter::calc_req_cap()
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{
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double total_cap = 0;
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// part 1: gate cap of 2 NOR gates
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// FIXME: need actual size
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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total_cap += 2*m_tech_param_ptr->calc_gatecap(WdecNORn+WdecNORp, 0);
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// part 2: inverter
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// FIXME: need actual size
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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total_cap += m_tech_param_ptr->calc_draincap(Wdecinvn, TechParameter::NCH, 1)
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+ m_tech_param_ptr->calc_draincap(Wdecinvp, TechParameter::PCH, 1)
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+ m_tech_param_ptr->calc_gatecap(Wdecinvn+Wdecinvp, 0);
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// part 3: wire cap
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double Cmetal = m_tech_param_ptr->get_Cmetal();
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total_cap += m_len_in_wire*Cmetal;
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return total_cap;
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}
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// switch cap of priority signal
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double RRArbiter::calc_pri_cap()
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{
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double total_cap = 0;
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// part 1: gate cap of NOR gate
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// FIXME: need actual size
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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total_cap += m_tech_param_ptr->calc_gatecap(WdecNORn+WdecNORp, 0);
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return total_cap;
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}
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// switch cap of grant signa
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double RRArbiter::calc_grant_cap()
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{
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double total_cap = 0;
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// part 1: drain cap of NOR gate
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// FIXME: need actual size
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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total_cap += 2*m_tech_param_ptr->calc_draincap(WdecNORn, TechParameter::NCH, 1)
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+ m_tech_param_ptr->calc_draincap(WdecNORp, TechParameter::PCH, 2);
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return total_cap;
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}
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// switch cap of carry signal
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double RRArbiter::calc_carry_cap()
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{
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double total_cap = 0;
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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// part 1: drain cap of NOR gate (this bloc)
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// FIXME: need actual size
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total_cap += 2*m_tech_param_ptr->calc_draincap(WdecNORn, TechParameter::NCH, 1)
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+ m_tech_param_ptr->calc_draincap(WdecNORp, TechParameter::PCH, 2);
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// part 2: gate cap of NOR gate (next block)
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// FIXME: need actual size
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total_cap += m_tech_param_ptr->calc_gatecap(WdecNORn+WdecNORp, 0);
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return total_cap;
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}
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// switch cap of internal carry node
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double RRArbiter::calc_carry_in_cap()
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{
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double total_cap = 0;
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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// part 1: gate cap of 2 NOR gate
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// FIXME: need actual size
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total_cap += 2*m_tech_param_ptr->calc_gatecap(WdecNORn+WdecNORp, 0);
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// part 2: drain cap of NOR gate (this bloc)
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// FIXME: need actual size
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total_cap += 2*m_tech_param_ptr->calc_draincap(WdecNORn, TechParameter::NCH, 1)
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+ m_tech_param_ptr->calc_draincap(WdecNORp, TechParameter::PCH, 2);
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return total_cap;
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}
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double RRArbiter::calc_i_static()
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{
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double i_static = 0;
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double WdecNORn = m_tech_param_ptr->get_WdecNORn();
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double WdecNORp = m_tech_param_ptr->get_WdecNORp();
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double Wdecinvn = m_tech_param_ptr->get_Wdecinvn();
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double Wdecinvp = m_tech_param_ptr->get_Wdecinvp();
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double Wdff = m_tech_param_ptr->get_Wdff();
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double NOR2_TAB_0 = m_tech_param_ptr->get_NOR2_TAB(0);
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double NOR2_TAB_1 = m_tech_param_ptr->get_NOR2_TAB(1);
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double NOR2_TAB_2 = m_tech_param_ptr->get_NOR2_TAB(2);
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double NOR2_TAB_3 = m_tech_param_ptr->get_NOR2_TAB(3);
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double NMOS_TAB_0 = m_tech_param_ptr->get_NMOS_TAB(0);
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double PMOS_TAB_0 = m_tech_param_ptr->get_PMOS_TAB(0);
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double DFF_TAB_0 = m_tech_param_ptr->get_DFF_TAB(0);
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// NOR
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i_static += (6*m_req_width*((WdecNORp*NOR2_TAB_0+WdecNORn*(NOR2_TAB_1+NOR2_TAB_2+NOR2_TAB_3))/4));
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// inverter
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i_static += 2*m_req_width*((Wdecinvn*NMOS_TAB_0+Wdecinvp*PMOS_TAB_0)/2);
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// dff
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i_static += m_req_width*Wdff*DFF_TAB_0;
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return i_static;
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}
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