c69d48f007
Ran all the source files through 'perl -pi' with this script: s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
247 lines
7.9 KiB
C++
247 lines
7.9 KiB
C++
/*
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* Copyright (c) 2007 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "config/full_system.hh"
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#if FULL_SYSTEM
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#include "arch/x86/interrupts.hh"
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#endif
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#include "arch/x86/regs/int.hh"
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#include "arch/x86/regs/misc.hh"
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#include "arch/x86/regs/segment.hh"
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#include "arch/x86/utility.hh"
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#include "arch/x86/x86_traits.hh"
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#include "cpu/base.hh"
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#include "sim/system.hh"
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namespace X86ISA {
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uint64_t
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getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
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{
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#if FULL_SYSTEM
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panic("getArgument() not implemented for x86!\n");
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#else
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panic("getArgument() only implemented for FULL_SYSTEM\n");
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M5_DUMMY_RETURN
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#endif
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}
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# if FULL_SYSTEM
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void initCPU(ThreadContext *tc, int cpuId)
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{
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// This function is essentially performing a reset. The actual INIT
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// interrupt does a subset of this, so we'll piggyback on some of its
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// functionality.
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InitInterrupt init(0);
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init.invoke(tc);
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PCState pc = tc->pcState();
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pc.upc(0);
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pc.nupc(1);
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tc->pcState(pc);
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// These next two loops zero internal microcode and implicit registers.
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// They aren't specified by the ISA but are used internally by M5's
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// implementation.
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for (int index = 0; index < NumMicroIntRegs; index++) {
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tc->setIntReg(INTREG_MICRO(index), 0);
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}
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for (int index = 0; index < NumImplicitIntRegs; index++) {
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tc->setIntReg(INTREG_IMPLICIT(index), 0);
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}
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// Set integer register EAX to 0 to indicate that the optional BIST
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// passed. No BIST actually runs, but software may still check this
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// register for errors.
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tc->setIntReg(INTREG_RAX, 0);
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tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
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tc->setMiscReg(MISCREG_CR8, 0);
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// TODO initialize x87, 64 bit, and 128 bit media state
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tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
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for (int i = 0; i < 8; i++) {
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tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
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tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
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}
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tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
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tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
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tc->setMiscReg(MISCREG_DEF_TYPE, 0);
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tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
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tc->setMiscReg(MISCREG_MCG_STATUS, 0);
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tc->setMiscReg(MISCREG_MCG_CTL, 0);
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for (int i = 0; i < 5; i++) {
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tc->setMiscReg(MISCREG_MC_CTL(i), 0);
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tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
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tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
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tc->setMiscReg(MISCREG_MC_MISC(i), 0);
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}
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tc->setMiscReg(MISCREG_TSC, 0);
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tc->setMiscReg(MISCREG_TSC_AUX, 0);
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for (int i = 0; i < 4; i++) {
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tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
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tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
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}
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tc->setMiscReg(MISCREG_STAR, 0);
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tc->setMiscReg(MISCREG_LSTAR, 0);
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tc->setMiscReg(MISCREG_CSTAR, 0);
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tc->setMiscReg(MISCREG_SF_MASK, 0);
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tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
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tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
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tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
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tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
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tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
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tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
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tc->setMiscReg(MISCREG_IORR_BASE0, 0);
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tc->setMiscReg(MISCREG_IORR_BASE1, 0);
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tc->setMiscReg(MISCREG_IORR_MASK0, 0);
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tc->setMiscReg(MISCREG_IORR_MASK1, 0);
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tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
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tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
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tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
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tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
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tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
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tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
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tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
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// Invalidate the caches (this should already be done for us)
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LocalApicBase lApicBase = 0;
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lApicBase.base = 0xFEE00000 >> 12;
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lApicBase.enable = 1;
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lApicBase.bsp = (cpuId == 0);
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tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
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Interrupts * interrupts = dynamic_cast<Interrupts *>(
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tc->getCpuPtr()->getInterruptController());
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assert(interrupts);
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interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
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interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
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interrupts->setClock(tc->getCpuPtr()->ticks(16));
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// TODO Set the SMRAM base address (SMBASE) to 0x00030000
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tc->setMiscReg(MISCREG_VM_CR, 0);
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tc->setMiscReg(MISCREG_IGNNE, 0);
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tc->setMiscReg(MISCREG_SMM_CTL, 0);
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tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
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}
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#endif
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void startupCPU(ThreadContext *tc, int cpuId)
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{
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#if FULL_SYSTEM
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if (cpuId == 0) {
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tc->activate(0);
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} else {
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// This is an application processor (AP). It should be initialized to
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// look like only the BIOS POST has run on it and put then put it into
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// a halted state.
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tc->suspend(0);
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}
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#else
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tc->activate(0);
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#endif
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}
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void
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copyMiscRegs(ThreadContext *src, ThreadContext *dest)
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{
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warn("copyMiscRegs is naively implemented for x86\n");
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for (int i = 0; i < NUM_MISCREGS; ++i) {
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if ( ( i != MISCREG_CR1 &&
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!(i > MISCREG_CR4 && i < MISCREG_CR8) &&
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!(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
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continue;
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}
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dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
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}
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}
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void
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copyRegs(ThreadContext *src, ThreadContext *dest)
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{
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panic("copyRegs not implemented for x86!\n");
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//copy int regs
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//copy float regs
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copyMiscRegs(src, dest);
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dest->pcState(src->pcState());
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}
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void
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skipFunction(ThreadContext *tc)
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{
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panic("Not implemented for x86\n");
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}
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} // namespace X86_ISA
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