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gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson fda338f8d3 Stats: Updates due to bus changes 
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
2012-07-09 12:35:41 -04:00

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---------- Begin Simulation Statistics ----------
sim_seconds 0.479151 # Number of seconds simulated
sim_ticks 479150606000 # Number of ticks simulated
final_tick 479150606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 194711 # Simulator instruction rate (inst/s)
host_op_rate 217215 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 60402792 # Simulator tick rate (ticks/s)
host_mem_usage 234724 # Number of bytes of host memory used
host_seconds 7932.59 # Real time elapsed on the host
sim_insts 1544563028 # Number of instructions simulated
sim_ops 1723073840 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 156296384 # Number of bytes read from this memory
system.physmem.bytes_read::total 156344896 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 71934976 # Number of bytes written to this memory
system.physmem.bytes_written::total 71934976 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2442131 # Number of read requests responded to by this memory
system.physmem.num_reads::total 2442889 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1123984 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1123984 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 101246 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 326194691 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 326295937 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 101246 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 101246 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 150130199 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 150130199 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 150130199 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 101246 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 326194691 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 476426136 # Total bandwidth to/from this memory (bytes/s)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.numCycles 958301213 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 302333500 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 248015603 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16105989 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 168718741 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 157776197 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 18362417 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 231 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 295110918 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2170236667 # Number of instructions fetch has processed
system.cpu.fetch.Branches 302333500 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 176138614 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 431684517 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 85621855 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 155290774 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 58 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 285908690 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 5538082 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 950817611 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.537566 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.220819 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 519133170 54.60% 54.60% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 23531871 2.47% 57.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38842821 4.09% 61.16% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 47928811 5.04% 66.20% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 41274787 4.34% 70.54% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 47187627 4.96% 75.50% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 39143273 4.12% 79.62% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 18340446 1.93% 81.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 175434805 18.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 950817611 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.315489 # Number of branch fetches per cycle
system.cpu.fetch.rate 2.264671 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 327140938 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 132753088 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 402950990 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 19241929 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 68730666 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 46279846 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 2359084469 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2481 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 68730666 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 349892865 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 63780880 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 14141 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 397813217 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 70585842 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2300380626 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 28739 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 5556251 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 56445912 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2275326533 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 10618275091 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 10618272387 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 2704 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 569006595 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 5461 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 5458 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 155601466 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 627528670 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 219567806 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 87006993 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 68089228 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2199559403 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1526 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2020307102 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 5002319 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 472139724 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1101721580 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 1355 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 950817611 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.124810 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.914497 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 272456432 28.65% 28.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 148972541 15.67% 44.32% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 161045064 16.94% 61.26% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 117808406 12.39% 73.65% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 124487858 13.09% 86.74% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 74416152 7.83% 94.57% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 38351621 4.03% 98.60% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 10558999 1.11% 99.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 2720538 0.29% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 950817611 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 866703 3.46% 3.46% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 4868 0.02% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 18978969 75.82% 79.30% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 5181359 20.70% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1236552318 61.21% 61.21% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 932322 0.05% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 41 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 588904292 29.15% 90.40% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 193918099 9.60% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2020307102 # Type of FU issued
system.cpu.iq.rate 2.108217 # Inst issue rate
system.cpu.iq.fu_busy_cnt 25031899 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.012390 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 5021465735 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2671886632 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1961215820 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 298 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 520 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 112 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2045338849 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 152 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 63654285 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 141601900 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 294123 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 189203 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 44720760 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 1137177 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 68730666 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 28026748 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1485770 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2199569564 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 5556141 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 627528670 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 219567806 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1463 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 343326 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 56332 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 189203 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 8602483 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 10215552 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18818035 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1990553449 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 574287819 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 29753653 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 8635 # number of nop insts executed
system.cpu.iew.exec_refs 765252053 # number of memory reference insts executed
system.cpu.iew.exec_branches 238421113 # Number of branches executed
system.cpu.iew.exec_stores 190964234 # Number of stores executed
system.cpu.iew.exec_rate 2.077169 # Inst execution rate
system.cpu.iew.wb_sent 1970075771 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1961215932 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1296581898 # num instructions producing a value
system.cpu.iew.wb_consumers 2068899277 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.046555 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.626701 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1544563046 # The number of committed instructions
system.cpu.commit.commitCommittedOps 1723073858 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 476570852 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16105557 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 882086946 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.953406 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.727739 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 391458685 44.38% 44.38% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 194911052 22.10% 66.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73858259 8.37% 74.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 35176751 3.99% 78.84% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 19156374 2.17% 81.01% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 30712442 3.48% 84.49% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 19230333 2.18% 86.67% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 11318069 1.28% 87.95% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 106264981 12.05% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 882086946 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1544563046 # Number of instructions committed
system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773816 # Number of memory references committed
system.cpu.commit.loads 485926770 # Number of loads committed
system.cpu.commit.membars 62 # Number of memory barriers committed
system.cpu.commit.branches 213462364 # Number of branches committed
system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions.
system.cpu.commit.function_calls 13665177 # Number of function calls committed.
system.cpu.commit.bw_lim_events 106264981 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 2975466076 # The number of ROB reads
system.cpu.rob.rob_writes 4468185114 # The number of ROB writes
system.cpu.timesIdled 802459 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7483602 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1544563028 # Number of Instructions Simulated
system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated
system.cpu.cpi 0.620435 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.620435 # CPI: Total CPI of All Threads
system.cpu.ipc 1.611772 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.611772 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9971004084 # number of integer regfile reads
system.cpu.int_regfile_writes 1941069131 # number of integer regfile writes
system.cpu.fp_regfile_reads 114 # number of floating regfile reads
system.cpu.fp_regfile_writes 123 # number of floating regfile writes
system.cpu.misc_regfile_reads 2910834876 # number of misc regfile reads
system.cpu.misc_regfile_writes 126 # number of misc regfile writes
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.tagsinuse 634.471646 # Cycle average of tags in use
system.cpu.icache.total_refs 285907562 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 789 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 362366.998733 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 634.471646 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.309801 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.309801 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 285907562 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 285907562 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 285907562 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 285907562 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 285907562 # number of overall hits
system.cpu.icache.overall_hits::total 285907562 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1128 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1128 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1128 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1128 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1128 # number of overall misses
system.cpu.icache.overall_misses::total 1128 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 40115500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 40115500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 40115500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 40115500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 40115500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 40115500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 285908690 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 285908690 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 285908690 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 285908690 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 285908690 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 285908690 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35563.386525 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 35563.386525 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 35563.386525 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 35563.386525 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 35563.386525 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 339 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 339 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 339 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 339 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 339 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 789 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 789 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 789 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 789 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 789 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 789 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28841500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 28841500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28841500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 28841500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28841500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 28841500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36554.499366 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36554.499366 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36554.499366 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 36554.499366 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9617864 # number of replacements
system.cpu.dcache.tagsinuse 4087.822620 # Cycle average of tags in use
system.cpu.dcache.total_refs 661858061 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9621960 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 68.786200 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 3369466000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 4087.822620 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.998004 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.998004 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 494463197 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 494463197 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 167394718 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 167394718 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 84 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 84 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 661857915 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 661857915 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 661857915 # number of overall hits
system.cpu.dcache.overall_hits::total 661857915 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 10787388 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 10787388 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 5191329 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 5191329 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 15978717 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 15978717 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 15978717 # number of overall misses
system.cpu.dcache.overall_misses::total 15978717 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 258680588500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 258680588500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 196204904993 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 196204904993 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 118500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 118500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 454885493493 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 454885493493 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 454885493493 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 454885493493 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 505250585 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 505250585 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 87 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 87 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 677836632 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 677836632 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 677836632 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 677836632 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021351 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.021351 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030080 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.030080 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034483 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034483 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.023573 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.023573 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.023573 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.023573 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23979.909548 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 23979.909548 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37794.735220 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 37794.735220 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 28468.211402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 28468.211402 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 28468.211402 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2516165984 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 147500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 424894 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5921.867534 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 16388.888889 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3474501 # number of writebacks
system.cpu.dcache.writebacks::total 3474501 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059372 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 3059372 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297385 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 3297385 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6356757 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6356757 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6356757 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6356757 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728016 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7728016 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893944 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1893944 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9621960 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9621960 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9621960 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9621960 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124261380000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 124261380000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91432769312 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 91432769312 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215694149312 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 215694149312 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215694149312 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 215694149312 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015295 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015295 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.014195 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014195 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.014195 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16079.337827 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16079.337827 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48276.384789 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48276.384789 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22416.861982 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22416.861982 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22416.861982 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22416.861982 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2427328 # number of replacements
system.cpu.l2cache.tagsinuse 31166.284891 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8745751 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2457039 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 3.559468 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 81028078000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 14024.049283 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 15.077840 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 17127.157769 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.427980 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.522679 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.951120 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 6116665 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6116695 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3474501 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3474501 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1063157 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1063157 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 7179822 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7179852 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 7179822 # number of overall hits
system.cpu.l2cache.overall_hits::total 7179852 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 759 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1611350 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1612109 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 830788 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 830788 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 759 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 2442138 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 2442897 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 759 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 2442138 # number of overall misses
system.cpu.l2cache.overall_misses::total 2442897 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27450000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 57809721000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 57837171000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 32456622937 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 32456622937 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 27450000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 90266343937 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 90293793937 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 27450000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 90266343937 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 90293793937 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 789 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7728015 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7728804 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3474501 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3474501 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893945 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1893945 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 789 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9621960 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9622749 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 789 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9621960 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9622749 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961977 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208508 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.208585 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438655 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.438655 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961977 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.253809 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.253867 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961977 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.253809 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.253867 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36166.007905 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35876.576163 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 35876.712431 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39067.274608 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39067.274608 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36166.007905 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36962.016044 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 36961.768727 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36166.007905 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36962.016044 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 36961.768727 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 23316238 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 2976 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7834.757392 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1123984 # number of writebacks
system.cpu.l2cache.writebacks::total 1123984 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits
system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611343 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1612101 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830788 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 830788 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 2442131 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 2442889 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 2442131 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 2442889 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25025500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52778176000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52803201500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29830819408 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29830819408 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25025500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 82608995408 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 82634020908 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25025500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 82608995408 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 82634020908 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208507 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208584 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438655 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438655 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.253866 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960710 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253808 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.253866 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33015.171504 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32754.153523 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32754.276252 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35906.656581 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35906.656581 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33015.171504 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33826.602835 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33826.351057 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
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