035b443093
arch/mips/isa/bitfields.def:
Add comment, move definition up in file
arch/mips/isa/decoder.def:
add basic arithmetic operations
arch/mips/isa/formats/fp.format:
change Integer -> FP words
arch/mips/isa/formats/int.format:
Add derived IntImm class
arch/mips/isa/operands.def:
change to MIPS sytle operands
--HG--
rename : arch/mips/isa/formats/fpop.format => arch/mips/isa/formats/fp.format
rename : arch/mips/isa/formats/integerop.format => arch/mips/isa/formats/int.format
extra : convert_revision : a95da47bc981e56a9898421da4eeb9c442d1dc15
111 lines
4.2 KiB
Plaintext
111 lines
4.2 KiB
Plaintext
////////////////////////////////////////////////////////////////////
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//
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// Floating Point operate instructions
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//
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output header {{
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/**
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* Base class for integer operations.
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*/
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class FPOp : public MipsStaticInst
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{
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protected:
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/// Constructor
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FPOp(const char *mnem, MachInst _machInst, OpClass __opClass) : MipsStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string FPOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return "Disassembly of integer instruction\n";
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}
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}};
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def template FPExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
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{
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//These are set to constants when the execute method
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//is generated
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bool useCc = ;
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bool checkPriv = ;
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//Attempt to execute the instruction
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try
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{
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checkPriv;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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}
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//If we have an exception for some reason,
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//deal with it
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catch(MipsException except)
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{
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//Deal with exception
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return No_Fault;
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}
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//Write the resulting state to the execution context
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%(op_wb)s;
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if(useCc)
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{
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xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
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xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
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xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
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xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
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xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
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xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
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xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
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xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
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}
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return No_Fault;
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}
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}};
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// Primary format for integer operate instructions:
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def format FPOp(code, *opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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checkPriv = (code.find('checkPriv') != -1)
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code.replace('checkPriv', '')
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if checkPriv:
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code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
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else:
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code.replace('checkPriv;', '')
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for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
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('xvValue', '0'), ('xcValue', '0')):
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code.replace(marker, value)
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iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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exec_output = IntegerExecute.subst(iop)
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}};
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// Primary format for integer operate instructions:
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def format FPOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
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orig_code = code
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cblk = CodeBlock(code)
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checkPriv = (code.find('checkPriv') != -1)
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code.replace('checkPriv', '')
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if checkPriv:
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code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
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else:
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code.replace('checkPriv;', '')
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for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
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('xvValue', xvValue), ('xcValue', xcValue)):
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code.replace(marker, value)
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iop = InstObjParams(name, Name, 'MipsStaticInst', cblk, opt_flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecodeWithMnemonic.subst(iop)
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exec_output = IntegerExecute.subst(iop)
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}};
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