3bc8cffc75
--HG-- extra : convert_revision : c90339248d1ee74df1c6b90a77ec9ea41f646311
246 lines
7.7 KiB
C++
246 lines
7.7 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include <sstream>
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#include <iostream>
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#include "cpu/base_cpu.hh"
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#include "base/cprintf.hh"
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#include "cpu/exec_context.hh"
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#include "base/misc.hh"
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#include "sim/param.hh"
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#include "sim/sim_events.hh"
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using namespace std;
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vector<BaseCPU *> BaseCPU::cpuList;
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// This variable reflects the max number of threads in any CPU. Be
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// careful to only use it once all the CPUs that you care about have
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// been initialized
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int maxThreadsPerCPU = 1;
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#ifdef FULL_SYSTEM
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BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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System *_system, Tick freq)
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: SimObject(_name), frequency(freq),
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number_of_threads(_number_of_threads), system(_system)
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#else
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BaseCPU::BaseCPU(const string &_name, int _number_of_threads,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads)
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: SimObject(_name), number_of_threads(_number_of_threads)
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#endif
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{
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// add self to global list of CPUs
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cpuList.push_back(this);
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if (number_of_threads > maxThreadsPerCPU)
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maxThreadsPerCPU = number_of_threads;
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// allocate per-thread instruction-based event queues
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comInstEventQueue = new (EventQueue *)[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comInstEventQueue[i] = new EventQueue("instruction-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (max_insts_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comInstEventQueue[i], max_insts_any_thread,
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"a thread reached the max instruction count");
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if (max_insts_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comInstEventQueue[i],
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"all threads reached the max instruction count",
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max_insts_all_threads, *counter);
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}
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// allocate per-thread load-based event queues
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comLoadEventQueue = new (EventQueue *)[number_of_threads];
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for (int i = 0; i < number_of_threads; ++i)
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comLoadEventQueue[i] = new EventQueue("load-based event queue");
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//
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// set up instruction-count-based termination events, if any
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//
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if (max_loads_any_thread != 0)
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for (int i = 0; i < number_of_threads; ++i)
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new SimExitEvent(comLoadEventQueue[i], max_loads_any_thread,
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"a thread reached the max load count");
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if (max_loads_all_threads != 0) {
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// allocate & initialize shared downcounter: each event will
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// decrement this when triggered; simulation will terminate
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// when counter reaches 0
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int *counter = new int;
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*counter = number_of_threads;
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for (int i = 0; i < number_of_threads; ++i)
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new CountedExitEvent(comLoadEventQueue[i],
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"all threads reached the max load count",
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max_loads_all_threads, *counter);
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}
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#ifdef FULL_SYSTEM
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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#endif
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}
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void
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BaseCPU::regStats()
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{
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int size = execContexts.size();
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if (size > 1) {
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for (int i = 0; i < size; ++i) {
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stringstream namestr;
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ccprintf(namestr, "%s.ctx%d", name(), i);
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execContexts[i]->regStats(namestr.str());
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}
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} else if (size == 1)
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execContexts[0]->regStats(name());
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}
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void
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BaseCPU::registerExecContexts()
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{
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *xc = execContexts[i];
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int cpu_id;
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#ifdef FULL_SYSTEM
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cpu_id = system->registerExecContext(xc);
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#else
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cpu_id = xc->process->registerExecContext(xc);
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#endif
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xc->cpu_id = cpu_id;
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}
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}
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void
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BaseCPU::switchOut()
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{
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// default: do nothing
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}
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void
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BaseCPU::takeOverFrom(BaseCPU *oldCPU)
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{
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assert(execContexts.size() == oldCPU->execContexts.size());
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for (int i = 0; i < execContexts.size(); ++i) {
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ExecContext *newXC = execContexts[i];
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ExecContext *oldXC = oldCPU->execContexts[i];
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newXC->takeOverFrom(oldXC);
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assert(newXC->cpu_id == oldXC->cpu_id);
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#ifdef FULL_SYSTEM
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system->replaceExecContext(newXC->cpu_id, newXC);
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#else
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assert(newXC->process == oldXC->process);
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newXC->process->replaceExecContext(newXC->cpu_id, newXC);
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#endif
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}
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#ifdef FULL_SYSTEM
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for (int i = 0; i < NumInterruptLevels; ++i)
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interrupts[i] = oldCPU->interrupts[i];
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intstatus = oldCPU->intstatus;
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#endif
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}
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#ifdef FULL_SYSTEM
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void
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BaseCPU::post_interrupt(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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AlphaISA::check_interrupts = 1;
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interrupts[int_num] |= 1 << index;
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intstatus |= (ULL(1) << int_num);
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}
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void
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BaseCPU::clear_interrupt(int int_num, int index)
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{
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DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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if (int_num < 0 || int_num >= NumInterruptLevels)
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panic("int_num out of bounds\n");
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if (index < 0 || index >= sizeof(uint64_t) * 8)
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panic("int_num out of bounds\n");
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interrupts[int_num] &= ~(1 << index);
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if (interrupts[int_num] == 0)
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intstatus &= ~(ULL(1) << int_num);
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}
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void
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BaseCPU::clear_interrupts()
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{
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DPRINTF(Interrupt, "Interrupts all cleared\n");
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memset(interrupts, 0, sizeof(interrupts));
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intstatus = 0;
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}
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#endif // FULL_SYSTEM
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//
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// This declaration is not needed now that SamplingCPU provides a
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// BaseCPUBuilder object.
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//
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#if 0
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DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)
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#endif
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