581bae9ecb
Expose MessageBuffers from SLICC controllers as SimObjects that can be manipulated in Python. This patch has numerous benefits: 1) First and foremost, it exposes MessageBuffers as SimObjects that can be manipulated in Python code. This allows parameters to be set and checked in Python code to avoid obfuscating parameters within protocol files. Further, now as SimObjects, MessageBuffer parameters are printed to config output files as a way to track parameters across simulations (e.g. buffer sizes) 2) Cleans up special-case code for responseFromMemory buffers, and aligns their instantiation and use with mandatoryQueue buffers. These two special buffers are the only MessageBuffers that are exposed to components outside of SLICC controllers, and they're both slave ends of these buffers. They should be exposed outside of SLICC in the same way, and this patch does it. 3) Distinguishes buffer-specific parameters from buffer-to-network parameters. Specifically, buffer size, randomization, ordering, recycle latency, and ports are all specific to a MessageBuffer, while the virtual network ID and type are intrinsics of how the buffer is connected to network ports. The former are specified in the Python object, while the latter are specified in the controller *.sm files. Unlike buffer-specific parameters, which may need to change depending on the simulated system structure, buffer-to-network parameters can be specified statically for most or all different simulated systems.
254 lines
10 KiB
Python
254 lines
10 KiB
Python
# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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import math
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import m5
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from m5.objects import *
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from m5.defines import buildEnv
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from m5.util import addToPath, fatal
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import MemConfig
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addToPath('../topologies')
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def define_options(parser):
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# By default, ruby uses the simple timing cpu
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parser.set_defaults(cpu_type="timing")
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parser.add_option("--ruby-clock", action="store", type="string",
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default='2GHz',
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help="Clock for blocks running at Ruby system's speed")
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parser.add_option("--access-backing-store", action="store_true", default=False,
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help="Should ruby maintain a second copy of memory")
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# Options related to cache structure
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parser.add_option("--ports", action="store", type="int", default=4,
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help="used of transitions per cycle which is a proxy \
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for the number of ports.")
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# ruby network options
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parser.add_option("--topology", type="string", default="Crossbar",
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help="check configs/topologies for complete set")
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parser.add_option("--mesh-rows", type="int", default=1,
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help="the number of rows in the mesh topology")
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parser.add_option("--garnet-network", type="choice",
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choices=['fixed', 'flexible'], help="'fixed'|'flexible'")
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parser.add_option("--network-fault-model", action="store_true", default=False,
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help="enable network fault model: see src/mem/ruby/network/fault_model/")
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# ruby mapping options
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parser.add_option("--numa-high-bit", type="int", default=0,
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help="high order address bit to use for numa mapping. " \
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"0 = highest bit, not specified = lowest bit")
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parser.add_option("--recycle-latency", type="int", default=10,
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help="Recycle latency for ruby controller input buffers")
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parser.add_option("--random_seed", type="int", default=1234,
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help="Used for seeding the random number generator")
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protocol = buildEnv['PROTOCOL']
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exec "import %s" % protocol
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eval("%s.define_options(parser)" % protocol)
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def setup_memory_controllers(system, ruby, dir_cntrls, options):
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ruby.block_size_bytes = options.cacheline_size
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ruby.memory_size_bits = 48
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block_size_bits = int(math.log(options.cacheline_size, 2))
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if options.numa_high_bit:
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numa_bit = options.numa_high_bit
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else:
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# if the numa_bit is not specified, set the directory bits as the
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# lowest bits above the block offset bits, and the numa_bit as the
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# highest of those directory bits
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dir_bits = int(math.log(options.num_dirs, 2))
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numa_bit = block_size_bits + dir_bits - 1
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index = 0
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mem_ctrls = []
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crossbars = []
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# Sets bits to be used for interleaving. Creates memory controllers
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# attached to a directory controller. A separate controller is created
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# for each address range as the abstract memory can handle only one
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# contiguous address range as of now.
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for dir_cntrl in dir_cntrls:
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dir_cntrl.directory.numa_high_bit = numa_bit
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crossbar = None
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if len(system.mem_ranges) > 1:
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crossbar = IOXBar()
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crossbars.append(crossbar)
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dir_cntrl.memory = crossbar.slave
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for r in system.mem_ranges:
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mem_ctrl = MemConfig.create_mem_ctrl(
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MemConfig.get(options.mem_type), r, index, options.num_dirs,
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int(math.log(options.num_dirs, 2)), options.cacheline_size)
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mem_ctrls.append(mem_ctrl)
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if crossbar != None:
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mem_ctrl.port = crossbar.master
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else:
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mem_ctrl.port = dir_cntrl.memory
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index += 1
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system.mem_ctrls = mem_ctrls
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if len(crossbars) > 0:
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ruby.crossbars = crossbars
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def create_topology(controllers, options):
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""" Called from create_system in configs/ruby/<protocol>.py
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Must return an object which is a subclass of BaseTopology
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found in configs/topologies/BaseTopology.py
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This is a wrapper for the legacy topologies.
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"""
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exec "import %s as Topo" % options.topology
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topology = eval("Topo.%s(controllers)" % options.topology)
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return topology
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def create_system(options, full_system, system, piobus = None, dma_ports = []):
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system.ruby = RubySystem()
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ruby = system.ruby
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# Set the network classes based on the command line options
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if options.garnet_network == "fixed":
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NetworkClass = GarnetNetwork_d
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IntLinkClass = GarnetIntLink_d
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ExtLinkClass = GarnetExtLink_d
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RouterClass = GarnetRouter_d
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InterfaceClass = GarnetNetworkInterface_d
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elif options.garnet_network == "flexible":
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NetworkClass = GarnetNetwork
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IntLinkClass = GarnetIntLink
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ExtLinkClass = GarnetExtLink
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RouterClass = GarnetRouter
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InterfaceClass = GarnetNetworkInterface
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else:
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NetworkClass = SimpleNetwork
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IntLinkClass = SimpleIntLink
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ExtLinkClass = SimpleExtLink
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RouterClass = Switch
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InterfaceClass = None
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# Instantiate the network object so that the controllers can connect to it.
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network = NetworkClass(ruby_system = ruby, topology = options.topology,
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routers = [], ext_links = [], int_links = [], netifs = [])
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ruby.network = network
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protocol = buildEnv['PROTOCOL']
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exec "import %s" % protocol
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try:
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(cpu_sequencers, dir_cntrls, topology) = \
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eval("%s.create_system(options, full_system, system, dma_ports,\
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ruby)"
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% protocol)
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except:
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print "Error: could not create sytem for ruby protocol %s" % protocol
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raise
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# Create a port proxy for connecting the system port. This is
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# independent of the protocol and kept in the protocol-agnostic
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# part (i.e. here).
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sys_port_proxy = RubyPortProxy(ruby_system = ruby)
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# Give the system port proxy a SimObject parent without creating a
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# full-fledged controller
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system.sys_port_proxy = sys_port_proxy
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# Connect the system port for loading of binaries etc
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system.system_port = system.sys_port_proxy.slave
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# Create the network topology
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topology.makeTopology(options, network, IntLinkClass, ExtLinkClass,
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RouterClass)
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if options.garnet_network is None:
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assert(NetworkClass == SimpleNetwork)
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assert(RouterClass == Switch)
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network.setup_buffers()
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if InterfaceClass != None:
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netifs = [InterfaceClass(id=i) for (i,n) in enumerate(network.ext_links)]
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network.netifs = netifs
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if options.network_fault_model:
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assert(options.garnet_network == "fixed")
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network.enable_fault_model = True
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network.fault_model = FaultModel()
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setup_memory_controllers(system, ruby, dir_cntrls, options)
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# Connect the cpu sequencers and the piobus
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if piobus != None:
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for cpu_seq in cpu_sequencers:
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cpu_seq.pio_master_port = piobus.slave
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cpu_seq.mem_master_port = piobus.slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu_seq.pio_slave_port = piobus.master
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ruby._cpu_ports = cpu_sequencers
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ruby.num_of_sequencers = len(cpu_sequencers)
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ruby.random_seed = options.random_seed
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# Create a backing copy of physical memory in case required
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if options.access_backing_store:
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ruby.access_backing_store = True
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ruby.phys_mem = SimpleMemory(range=system.mem_ranges[0],
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in_addr_map=False)
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def send_evicts(options):
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# currently, 2 scenarios warrant forwarding evictions to the CPU:
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# 1. The O3 model must keep the LSQ coherent with the caches
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# 2. The x86 mwait instruction is built on top of coherence invalidations
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if options.cpu_type == "detailed" or buildEnv['TARGET_ISA'] == 'x86':
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return True
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return False
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