85e8779de7
This patch enables tracking of cache occupancy per thread along with ages (in buckets) per cache blocks. Cache occupancy stats are recalculated on each stat dump.
756 lines
20 KiB
C++
756 lines
20 KiB
C++
/*
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* Copyright (c) 2010-2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Steve Reinhardt
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*/
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#include <string>
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#include <vector>
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#include "arch/arm/faults.hh"
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#include "arch/arm/pagetable.hh"
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#include "arch/arm/system.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "arch/arm/utility.hh"
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#include "base/inifile.hh"
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#include "base/str.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Checkpoint.hh"
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#include "debug/TLB.hh"
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#include "debug/TLBVerbose.hh"
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#include "mem/page_table.hh"
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#include "params/ArmTLB.hh"
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#include "sim/full_system.hh"
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#include "sim/process.hh"
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using namespace std;
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using namespace ArmISA;
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TLB::TLB(const Params *p)
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: BaseTLB(p), size(p->size) , tableWalker(p->walker),
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rangeMRU(1), bootUncacheability(false), miscRegValid(false)
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{
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table = new TlbEntry[size];
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memset(table, 0, sizeof(TlbEntry) * size);
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tableWalker->setTlb(this);
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}
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TLB::~TLB()
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{
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if (table)
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delete [] table;
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}
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bool
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TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
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{
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if (!miscRegValid)
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updateMiscReg(tc);
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TlbEntry *e = lookup(va, contextId, true);
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if (!e)
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return false;
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pa = e->pAddr(va);
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return true;
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}
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Fault
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TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
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{
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return NoFault;
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}
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TlbEntry*
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TLB::lookup(Addr va, uint8_t cid, bool functional)
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{
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TlbEntry *retval = NULL;
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// Maitaining LRU array
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int x = 0;
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while (retval == NULL && x < size) {
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if (table[x].match(va, cid)) {
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// We only move the hit entry ahead when the position is higher than rangeMRU
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if (x > rangeMRU && !functional) {
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TlbEntry tmp_entry = table[x];
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for(int i = x; i > 0; i--)
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table[i] = table[i-1];
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table[0] = tmp_entry;
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retval = &table[0];
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} else {
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retval = &table[x];
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}
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break;
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}
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x++;
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}
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DPRINTF(TLBVerbose, "Lookup %#x, cid %#x -> %s ppn %#x size: %#x pa: %#x ap:%d\n",
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va, cid, retval ? "hit" : "miss", retval ? retval->pfn : 0,
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retval ? retval->size : 0, retval ? retval->pAddr(va) : 0,
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retval ? retval->ap : 0);
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;
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return retval;
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}
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// insert a new TLB entry
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void
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TLB::insert(Addr addr, TlbEntry &entry)
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{
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DPRINTF(TLB, "Inserting entry into TLB with pfn:%#x size:%#x vpn: %#x"
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" asid:%d N:%d global:%d valid:%d nc:%d sNp:%d xn:%d ap:%#x"
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" domain:%#x\n", entry.pfn, entry.size, entry.vpn, entry.asid,
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entry.N, entry.global, entry.valid, entry.nonCacheable, entry.sNp,
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entry.xn, entry.ap, entry.domain);
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if (table[size-1].valid)
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DPRINTF(TLB, " - Replacing Valid entry %#x, asn %d ppn %#x size: %#x ap:%d\n",
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table[size-1].vpn << table[size-1].N, table[size-1].asid,
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table[size-1].pfn << table[size-1].N, table[size-1].size,
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table[size-1].ap);
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//inserting to MRU position and evicting the LRU one
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for(int i = size-1; i > 0; i--)
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table[i] = table[i-1];
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table[0] = entry;
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inserts++;
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}
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void
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TLB::printTlb()
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{
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int x = 0;
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TlbEntry *te;
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DPRINTF(TLB, "Current TLB contents:\n");
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while (x < size) {
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te = &table[x];
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if (te->valid)
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DPRINTF(TLB, " * %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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x++;
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}
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}
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void
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TLB::flushAll()
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{
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DPRINTF(TLB, "Flushing all TLB entries\n");
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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if (te->valid) {
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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flushedEntries++;
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}
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x++;
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}
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memset(table, 0, sizeof(TlbEntry) * size);
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flushTlb++;
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}
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void
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TLB::flushMvaAsid(Addr mva, uint64_t asn)
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{
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DPRINTF(TLB, "Flushing mva %#x asid: %#x\n", mva, asn);
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TlbEntry *te;
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te = lookup(mva, asn);
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while (te != NULL) {
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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te->valid = false;
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flushedEntries++;
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te = lookup(mva,asn);
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}
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flushTlbMvaAsid++;
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}
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void
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TLB::flushAsid(uint64_t asn)
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{
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DPRINTF(TLB, "Flushing all entries with asid: %#x\n", asn);
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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if (te->asid == asn) {
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te->valid = false;
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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flushedEntries++;
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}
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x++;
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}
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flushTlbAsid++;
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}
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void
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TLB::flushMva(Addr mva)
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{
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DPRINTF(TLB, "Flushing all entries with mva: %#x\n", mva);
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int x = 0;
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TlbEntry *te;
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while (x < size) {
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te = &table[x];
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Addr v = te->vpn << te->N;
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if (mva >= v && mva < v + te->size) {
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te->valid = false;
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DPRINTF(TLB, " - %#x, asn %d ppn %#x size: %#x ap:%d\n",
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te->vpn << te->N, te->asid, te->pfn << te->N, te->size, te->ap);
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flushedEntries++;
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}
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x++;
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}
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flushTlbMva++;
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}
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void
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TLB::drainResume()
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{
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// We might have unserialized something or switched CPUs, so make
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// sure to re-read the misc regs.
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miscRegValid = false;
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}
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void
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TLB::serialize(ostream &os)
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{
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DPRINTF(Checkpoint, "Serializing Arm TLB\n");
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SERIALIZE_SCALAR(_attr);
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int num_entries = size;
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SERIALIZE_SCALAR(num_entries);
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for(int i = 0; i < size; i++){
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nameOut(os, csprintf("%s.TlbEntry%d", name(), i));
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table[i].serialize(os);
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}
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}
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void
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TLB::unserialize(Checkpoint *cp, const string §ion)
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{
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DPRINTF(Checkpoint, "Unserializing Arm TLB\n");
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UNSERIALIZE_SCALAR(_attr);
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int num_entries;
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UNSERIALIZE_SCALAR(num_entries);
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for(int i = 0; i < min(size, num_entries); i++){
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table[i].unserialize(cp, csprintf("%s.TlbEntry%d", section, i));
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}
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}
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void
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TLB::regStats()
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{
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instHits
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.name(name() + ".inst_hits")
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.desc("ITB inst hits")
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;
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instMisses
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.name(name() + ".inst_misses")
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.desc("ITB inst misses")
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;
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instAccesses
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.name(name() + ".inst_accesses")
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.desc("ITB inst accesses")
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;
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readHits
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.name(name() + ".read_hits")
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.desc("DTB read hits")
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;
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readMisses
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.name(name() + ".read_misses")
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.desc("DTB read misses")
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;
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readAccesses
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.name(name() + ".read_accesses")
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.desc("DTB read accesses")
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;
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writeHits
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.name(name() + ".write_hits")
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.desc("DTB write hits")
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;
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writeMisses
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.name(name() + ".write_misses")
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.desc("DTB write misses")
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;
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writeAccesses
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.name(name() + ".write_accesses")
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.desc("DTB write accesses")
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;
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hits
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.name(name() + ".hits")
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.desc("DTB hits")
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;
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misses
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.name(name() + ".misses")
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.desc("DTB misses")
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;
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accesses
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.name(name() + ".accesses")
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.desc("DTB accesses")
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;
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flushTlb
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.name(name() + ".flush_tlb")
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.desc("Number of times complete TLB was flushed")
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;
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flushTlbMva
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.name(name() + ".flush_tlb_mva")
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.desc("Number of times TLB was flushed by MVA")
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;
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flushTlbMvaAsid
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.name(name() + ".flush_tlb_mva_asid")
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.desc("Number of times TLB was flushed by MVA & ASID")
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;
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flushTlbAsid
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.name(name() + ".flush_tlb_asid")
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.desc("Number of times TLB was flushed by ASID")
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;
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flushedEntries
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.name(name() + ".flush_entries")
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.desc("Number of entries that have been flushed from TLB")
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;
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alignFaults
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.name(name() + ".align_faults")
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.desc("Number of TLB faults due to alignment restrictions")
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;
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prefetchFaults
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.name(name() + ".prefetch_faults")
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.desc("Number of TLB faults due to prefetch")
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;
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domainFaults
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.name(name() + ".domain_faults")
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.desc("Number of TLB faults due to domain restrictions")
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;
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permsFaults
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.name(name() + ".perms_faults")
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.desc("Number of TLB faults due to permissions restrictions")
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;
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instAccesses = instHits + instMisses;
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readAccesses = readHits + readMisses;
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writeAccesses = writeHits + writeMisses;
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hits = readHits + writeHits + instHits;
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misses = readMisses + writeMisses + instMisses;
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accesses = readAccesses + writeAccesses + instAccesses;
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}
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Fault
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TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing)
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{
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if (!miscRegValid)
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updateMiscReg(tc);
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Addr vaddr = req->getVaddr();
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uint32_t flags = req->getFlags();
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bool is_fetch = (mode == Execute);
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bool is_write = (mode == Write);
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if (!is_fetch) {
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assert(flags & MustBeOne);
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if (sctlr.a || !(flags & AllowUnaligned)) {
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if (vaddr & flags & AlignmentMask) {
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return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
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}
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}
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}
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Addr paddr;
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Process *p = tc->getProcessPtr();
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if (!p->pTable->translate(vaddr, paddr))
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return Fault(new GenericPageTableFault(vaddr));
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req->setPaddr(paddr);
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return NoFault;
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}
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Fault
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TLB::trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp)
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{
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return NoFault;
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}
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Fault
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TLB::walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
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bool is_write, uint8_t domain, bool sNp)
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{
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return NoFault;
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}
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Fault
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TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing, bool functional)
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{
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// No such thing as a functional timing access
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assert(!(timing && functional));
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if (!miscRegValid) {
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updateMiscReg(tc);
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DPRINTF(TLBVerbose, "TLB variables changed!\n");
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}
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Addr vaddr = req->getVaddr();
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uint32_t flags = req->getFlags();
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bool is_fetch = (mode == Execute);
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bool is_write = (mode == Write);
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bool is_priv = isPriv && !(flags & UserMode);
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req->setAsid(contextId.asid);
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if (is_priv)
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req->setFlags(Request::PRIVILEGED);
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req->taskId(tc->getCpuPtr()->taskId());
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DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n",
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isPriv, flags & UserMode);
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// If this is a clrex instruction, provide a PA of 0 with no fault
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// This will force the monitor to set the tracked address to 0
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// a bit of a hack but this effectively clrears this processors monitor
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if (flags & Request::CLEAR_LL){
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req->setPaddr(0);
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req->setFlags(Request::UNCACHEABLE);
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req->setFlags(Request::CLEAR_LL);
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return NoFault;
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}
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if ((req->isInstFetch() && (!sctlr.i)) ||
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((!req->isInstFetch()) && (!sctlr.c))){
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req->setFlags(Request::UNCACHEABLE);
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}
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if (!is_fetch) {
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assert(flags & MustBeOne);
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if (sctlr.a || !(flags & AllowUnaligned)) {
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if (vaddr & flags & AlignmentMask) {
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alignFaults++;
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return new DataAbort(vaddr, 0, is_write, ArmFault::AlignmentFault);
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}
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}
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}
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Fault fault;
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if (!sctlr.m) {
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req->setPaddr(vaddr);
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if (sctlr.tre == 0) {
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req->setFlags(Request::UNCACHEABLE);
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} else {
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if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2)
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req->setFlags(Request::UNCACHEABLE);
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}
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// Set memory attributes
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TlbEntry temp_te;
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tableWalker->memAttrs(tc, temp_te, sctlr, 0, 1);
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temp_te.shareable = true;
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DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
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%d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable,
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temp_te.innerAttrs, temp_te.outerAttrs);
|
|
setAttr(temp_te.attributes);
|
|
|
|
return trickBoxCheck(req, mode, 0, false);
|
|
}
|
|
|
|
DPRINTF(TLBVerbose, "Translating vaddr=%#x context=%d\n", vaddr, contextId);
|
|
// Translation enabled
|
|
|
|
TlbEntry *te = lookup(vaddr, contextId);
|
|
if (te == NULL) {
|
|
if (req->isPrefetch()){
|
|
//if the request is a prefetch don't attempt to fill the TLB
|
|
//or go any further with the memory access
|
|
prefetchFaults++;
|
|
return new PrefetchAbort(vaddr, ArmFault::PrefetchTLBMiss);
|
|
}
|
|
|
|
if (is_fetch)
|
|
instMisses++;
|
|
else if (is_write)
|
|
writeMisses++;
|
|
else
|
|
readMisses++;
|
|
|
|
// start translation table walk, pass variables rather than
|
|
// re-retreaving in table walker for speed
|
|
DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
|
|
vaddr, contextId);
|
|
fault = tableWalker->walk(req, tc, contextId, mode, translation,
|
|
timing, functional);
|
|
if (timing && fault == NoFault) {
|
|
delay = true;
|
|
// for timing mode, return and wait for table walk
|
|
return fault;
|
|
}
|
|
if (fault)
|
|
return fault;
|
|
|
|
te = lookup(vaddr, contextId);
|
|
if (!te)
|
|
printTlb();
|
|
assert(te);
|
|
} else {
|
|
if (is_fetch)
|
|
instHits++;
|
|
else if (is_write)
|
|
writeHits++;
|
|
else
|
|
readHits++;
|
|
}
|
|
|
|
// Set memory attributes
|
|
DPRINTF(TLBVerbose,
|
|
"Setting memory attributes: shareable: %d, innerAttrs: %d, \
|
|
outerAttrs: %d\n",
|
|
te->shareable, te->innerAttrs, te->outerAttrs);
|
|
setAttr(te->attributes);
|
|
if (te->nonCacheable) {
|
|
req->setFlags(Request::UNCACHEABLE);
|
|
|
|
// Prevent prefetching from I/O devices.
|
|
if (req->isPrefetch()) {
|
|
return new PrefetchAbort(vaddr, ArmFault::PrefetchUncacheable);
|
|
}
|
|
}
|
|
|
|
if (!bootUncacheability &&
|
|
((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
|
|
req->setFlags(Request::UNCACHEABLE);
|
|
|
|
switch ( (dacr >> (te->domain * 2)) & 0x3) {
|
|
case 0:
|
|
domainFaults++;
|
|
DPRINTF(TLB, "TLB Fault: Data abort on domain. DACR: %#x domain: %#x"
|
|
" write:%d sNp:%d\n", dacr, te->domain, is_write, te->sNp);
|
|
if (is_fetch)
|
|
return new PrefetchAbort(vaddr,
|
|
(te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
|
|
else
|
|
return new DataAbort(vaddr, te->domain, is_write,
|
|
(te->sNp ? ArmFault::Domain0 : ArmFault::Domain1));
|
|
case 1:
|
|
// Continue with permissions check
|
|
break;
|
|
case 2:
|
|
panic("UNPRED domain\n");
|
|
case 3:
|
|
req->setPaddr(te->pAddr(vaddr));
|
|
fault = trickBoxCheck(req, mode, te->domain, te->sNp);
|
|
if (fault)
|
|
return fault;
|
|
return NoFault;
|
|
}
|
|
|
|
uint8_t ap = te->ap;
|
|
|
|
if (sctlr.afe == 1)
|
|
ap |= 1;
|
|
|
|
bool abt;
|
|
|
|
/* if (!sctlr.xp)
|
|
ap &= 0x3;
|
|
*/
|
|
switch (ap) {
|
|
case 0:
|
|
DPRINTF(TLB, "Access permissions 0, checking rs:%#x\n", (int)sctlr.rs);
|
|
if (!sctlr.xp) {
|
|
switch ((int)sctlr.rs) {
|
|
case 2:
|
|
abt = is_write;
|
|
break;
|
|
case 1:
|
|
abt = is_write || !is_priv;
|
|
break;
|
|
case 0:
|
|
case 3:
|
|
default:
|
|
abt = true;
|
|
break;
|
|
}
|
|
} else {
|
|
abt = true;
|
|
}
|
|
break;
|
|
case 1:
|
|
abt = !is_priv;
|
|
break;
|
|
case 2:
|
|
abt = !is_priv && is_write;
|
|
break;
|
|
case 3:
|
|
abt = false;
|
|
break;
|
|
case 4:
|
|
panic("UNPRED premissions\n");
|
|
case 5:
|
|
abt = !is_priv || is_write;
|
|
break;
|
|
case 6:
|
|
case 7:
|
|
abt = is_write;
|
|
break;
|
|
default:
|
|
panic("Unknown permissions\n");
|
|
}
|
|
if ((is_fetch) && (abt || te->xn)) {
|
|
permsFaults++;
|
|
DPRINTF(TLB, "TLB Fault: Prefetch abort on permission check. AP:%d priv:%d"
|
|
" write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
|
|
return new PrefetchAbort(vaddr,
|
|
(te->sNp ? ArmFault::Permission0 :
|
|
ArmFault::Permission1));
|
|
} else if (abt) {
|
|
permsFaults++;
|
|
DPRINTF(TLB, "TLB Fault: Data abort on permission check. AP:%d priv:%d"
|
|
" write:%d sNp:%d\n", ap, is_priv, is_write, te->sNp);
|
|
return new DataAbort(vaddr, te->domain, is_write,
|
|
(te->sNp ? ArmFault::Permission0 :
|
|
ArmFault::Permission1));
|
|
}
|
|
|
|
req->setPaddr(te->pAddr(vaddr));
|
|
// Check for a trickbox generated address fault
|
|
fault = trickBoxCheck(req, mode, te->domain, te->sNp);
|
|
if (fault)
|
|
return fault;
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
Fault
|
|
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
bool delay = false;
|
|
Fault fault;
|
|
if (FullSystem)
|
|
fault = translateFs(req, tc, mode, NULL, delay, false);
|
|
else
|
|
fault = translateSe(req, tc, mode, NULL, delay, false);
|
|
assert(!delay);
|
|
return fault;
|
|
}
|
|
|
|
Fault
|
|
TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
|
|
{
|
|
bool delay = false;
|
|
Fault fault;
|
|
if (FullSystem)
|
|
fault = translateFs(req, tc, mode, NULL, delay, false, true);
|
|
else
|
|
fault = translateSe(req, tc, mode, NULL, delay, false);
|
|
assert(!delay);
|
|
return fault;
|
|
}
|
|
|
|
Fault
|
|
TLB::translateTiming(RequestPtr req, ThreadContext *tc,
|
|
Translation *translation, Mode mode)
|
|
{
|
|
assert(translation);
|
|
bool delay = false;
|
|
Fault fault;
|
|
if (FullSystem)
|
|
fault = translateFs(req, tc, mode, translation, delay, true);
|
|
else
|
|
fault = translateSe(req, tc, mode, translation, delay, true);
|
|
DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
|
|
NoFault);
|
|
if (!delay)
|
|
translation->finish(fault, req, tc, mode);
|
|
else
|
|
translation->markDelayed();
|
|
return fault;
|
|
}
|
|
|
|
BaseMasterPort*
|
|
TLB::getMasterPort()
|
|
{
|
|
return &tableWalker->getMasterPort("port");
|
|
}
|
|
|
|
|
|
|
|
ArmISA::TLB *
|
|
ArmTLBParams::create()
|
|
{
|
|
return new ArmISA::TLB(this);
|
|
}
|