409 lines
16 KiB
C
409 lines
16 KiB
C
#ifndef __DECCHIP21040_H_LOADED
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#define __DECCHIP21040_H_LOADED
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/*****************************************************************************
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Copyright © 1993, 1994 Digital Equipment Corporation,
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Maynard, Massachusetts.
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All Rights Reserved
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Permission to use, copy, modify, and distribute this software and its
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documentation for any purpose and without fee is hereby granted, provided
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that the copyright notice and this permission notice appear in all copies
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of software and supporting documentation, and that the name of Digital not
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be used in advertising or publicity pertaining to distribution of the software
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without specific, written prior permission. Digital grants this permission
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provided that you prominently mark, as not part of the original, any
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modifications made to this software or documentation.
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Digital Equipment Corporation disclaims all warranties and/or guarantees
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with regard to this software, including all implied warranties of fitness for
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a particular purpose and merchantability, and makes no representations
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regarding the use of, or the results of the use of, the software and
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documentation in terms of correctness, accuracy, reliability, currentness or
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otherwise; and you rely on the software, documentation and results solely at
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your own risk.
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******************************************************************************/
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/*
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* $Id: DEC21040.h,v 1.1.1.1 1997/10/30 23:27:13 verghese Exp $
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*/
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/*
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* MODULE DESCRIPTION:
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*
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* Parameters and logicals for AM79C960 drivers in EB64 monitor
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*
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* HISTORY:
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*
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* $Log:
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*
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*/
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#ifdef NEEDPCI
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#include "pci.h"
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/* The embedded Ethernet controller on the EB66 and EB64+ is a
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* DECchip 21040 PCI device.
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*
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* Please see the PCI and DECchip 21040 literature for definitive lists
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* and further detail.
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*
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*/
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/*****************************************************************************
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* General *
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*****************************************************************************/
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/*
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* Maximum number of DECchip 21040s supported in the EB66 and
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* 64+ monitors. This is assuming 1 embedded device and 2 PCI
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* slots. Of course this changes if a bridge card is used.
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*/
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#define DECCHIP21040_MAX_DEVICES 3
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/*****************************************************************************
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* ROM ID *
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*****************************************************************************/
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/*
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* As the ROM ID is only used by the DECchip 21040, then this information
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* can go here. Note that this information is the same for both EB66
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* and EB64P.
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*
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* To read this device you must first write which page you want
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* into the PAGE_REGISTER. The bit settings look like:
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*
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* SxxA AAAA
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*
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* Where S = 0 = BBRAM, S = 1 = Ethernet ID ROM.
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*
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* A AAAA select the high order address lines of the BBRAM
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* and are ignored for the Ethernet ID ROM.
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*/
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#define PAGE_REGISTER 0xc00
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#define SELECT_ROMID 0x80
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#define ROMID_BASE 0x800
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/*****************************************************************************
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* CSRs, these exist in PCI I/O space *
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*****************************************************************************/
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/*
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* CSR offsets.
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*/
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#define CSR0 0x0000 /* Bus Mode Register */
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#define CSR1 0x0008 /* Transmit Poll Demand */
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#define CSR2 0x0010 /* Receive Poll Demand */
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#define CSR3 0x0018 /* Rx Ring Base Address */
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#define CSR4 0x0020 /* Tx Ring Base Address */
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#define CSR5 0x0028 /* Status Register */
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#define CSR6 0x0030 /* Serial command register */
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#define CSR7 0x0038 /* Interrupt Mask register */
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#define CSR8 0x0040 /* Missed Frame counter */
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#define CSR9 0x0048 /* ENET ROM register */
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#define CSR10 0x0050 /* Data Diagnostic register */
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#define CSR11 0x0058 /* Full duplex register */
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#define CSR12 0x0060 /* SIA Status register */
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#define CSR13 0x0068 /* SIA connectivity register */
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#define CSR14 0x0070 /* SIA Tx Rx Register */
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#define CSR15 0x0078 /* SIA General register */
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#define TDES1_ADD 0x0088
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#define RDES1_ADD 0x00B8
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#define PCI_DIAG 0x0178
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/*
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* CSR bit definitions (see the DECchip 21040 manual for details).
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*/
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#define CSR0_CAL 0x0000C000 /* 15:14 Cache alignment */
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#define CSR0_PBL 0x00003F00 /* 13:18 Programmable burst length */
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#define CSR0_BLE 0x00000080 /* Big/Little endian */
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#define CSR0_DSL 0x0000007C /* Descriptor Skip Length */
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#define CSR0_BAR 0x00000020 /* Bus Arbitration */
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#define CSR0_SWR 0x00000001 /* Software Reset */
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#define CSR1_TPD 0x00000001 /* Transmit Poll Demand */
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#define CSR2_RPD 0x00000001 /* Receive Poll Demand */
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#define CSR3_RXB 0xFFFFFFFC /* Rx ring base address */
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#define CSR4_TXB 0xFFFFFFFC /* Tx ring base address */
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#define CSR5_EB 0x03800000 /* 25:23 Error Bits */
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#define CSR5_TS 0x00700000 /* 22:20 Transmission Process State */
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#define CSR5_RS 0x000E0000 /* 19:17 Receive Process State */
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#define CSR5_NIS 0x00010000 /* Normal interrupt Summary */
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#define CSR5_AIS 0x00008000 /* Abnormal interrupt Summary */
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#define CSR5_SE 0x00002000 /* System Error */
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#define CSR5_LNF 0x00001000 /* link fail */
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#define CSR5_FD 0x00000800 /* Full duplex short frame received */
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#define CSR5_AT 0x00000400 /* AUI/TP switch */
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#define CSR5_RWT 0x00000200 /* Receive watchdog time-out */
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#define CSR5_RPS 0x00000100 /* Receive process stopped */
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#define CSR5_RU 0x00000080 /* Receive buffer unavailable */
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#define CSR5_RI 0x00000040 /* Receive Interrupt */
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#define CSR5_UNF 0x00000020 /* Transmit underflow */
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#define CSR5_TJT 0x00000008 /* Transmit jabber timeout */
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#define CSR5_TU 0x00000004 /* Transmit buffer unavailable */
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#define CSR5_TPS 0x00000002 /* Transmit process stopped */
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#define CSR5_TI 0x00000001 /* Transmit interrupt */
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#define CSR5_TS_SUSPENDED 0x00600000 /* 110: Transmit process suspended */
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#define CSR5_RS_SUSPENDED 0x00080000 /* 100: Receive process suspended */
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#define CSR6_TR 0x0000C000 /* 15:14 Threshold control bits */
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#define CSR6_ST 0x00002000 /* Start/stop transmission */
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#define CSR6_FC 0x00001000 /* Force collision mode */
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#define CSR6_OM 0x00000C00 /* 11:10 Operating Mode */
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#define CSR6_FD 0x00000200 /* Full duplex operating mode */
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#define CSR6_FKD 0x00000100 /* Flaky oscillator disable */
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#define CSR6_PM 0x00000080 /* Pass All Multicast */
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#define CSR6_PR 0x00000040 /* Promiscuous mode */
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#define CSR6_SB 0x00000020 /* Start/Stop Backoff counter */
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#define CSR6_IF 0x00000010 /* Inverse filtering */
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#define CSR6_PB 0x00000008 /* Pass Bad frames */
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#define CSR6_SR 0x00000002 /* Start/Stop Receive */
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#define CSR6_HP 0x00000001 /* Hash/Perfect receive filtering mode
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*/
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#define CSR7_NIM 0x00010000 /* Normal interrupt summary mask */
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#define CSR7_AIM 0x00008000 /* Abnormal interrupt summary mask */
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#define CSR7_SEM 0x00002000 /* System Error Mask */
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#define CSR7_LFM 0x00001000 /* Link fail mask */
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#define CSR7_FDM 0x00000800 /* Full Duplex mask */
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#define CSR7_ATM 0x00000400 /* AUI/TP switch mask */
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#define CSR7_RWM 0x00000200 /* Receive watchdog timeout mask */
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#define CSR7_RSM 0x00000100 /* Receive stopped mask */
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#define CSR7_RUM 0x00000080 /* Receive buffer unavailable mask */
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#define CSR7_RIM 0x00000040 /* Receive interrupt mask */
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#define CSR7_UNM 0x00000020 /* Underflow interrupt mask */
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#define CSR7_TJM 0x00000008 /* transmit jabber timeout mask */
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#define CSR7_TUM 0x00000004 /* transmit buffer unavailable mask */
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#define CSR7_TSM 0x00000002 /* transmission stopped mask */
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#define CSR7_TIM 0x00000001 /* transmit interrupt mask */
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#define CSR8_MFO 0x00010000 /* Missed frame overflow */
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#define CSR8_MFC 0x0000FFFF /* Missed frame counter */
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#define CSR9_DT 0x000000FF /* 7:0 Data */
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#define CSR9_DN 0x80000000 /* 31 Data not valid, 0 = valid */
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#define CSR11_FD 0x0000FFFF /* 15:0 Full duplex auto configuration
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* value */
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#define CSR12_PAUI 0x00000001
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#define CSR12_NCR 0x00000002
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#define CSR12_LKF 0x00000004
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/*
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* CSR13 - SIA programming.
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*/
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#define CSR13_SRL 0x00000001 /* SIA Reset r/w */
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#define CSR13_PS 0x00000002 /* Pin AUI/TP Selection r/w */
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#define CSR13_CAC 0x00000004 /* CSR Auto Configuration */
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#define CSR13_AUI 0x00000008 /* 10 Base T or AUI */
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#define CSR13_EDP 0x00000010 /* SIA PLL external input enable */
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#define CSR13_ENI 0x00000020 /* Encoder Input Mux */
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#define CSR13_SIM 0x00000040 /* Serial Interface Input Mux */
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/*****************************************************************************
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* Macros *
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*****************************************************************************/
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#define _21040WriteCSR(device,csr,value) \
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(outportl((device)->PCI_IO_Base + (csr), (value)))
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#define _21040ReadCSR(device,csr) \
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(inportl((device)->PCI_IO_Base + (csr)))
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#define _21040ValidBuffer(buffer,size) \
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( \
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(((unsigned long)(buffer) & 0x3) == 0) \
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&& \
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((unsigned long)(buffer) <= 0xFFFFFFFF) \
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&& \
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(PCIValidAddress((unsigned char *) (buffer))) \
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&& \
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(PCIValidAddress((unsigned char *) (buffer) + (size))) \
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)
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/*****************************************************************************
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* PCI Constants *
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*****************************************************************************/
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/*
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* The configuration registers for DECchip 21040 exist in PCI configuration
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* space. The definitions for the standard fields are in pci.h, these
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* definitions are 21040 specific.
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*/
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#define CFID 0x0000 /* Configuration ID */
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#define CFCS 0x0004 /* Configuration command/status */
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#define CFRV 0x0008 /* Configuration revision */
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#define CFLT 0x000C /* Configuration latency timer */
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#define CBIO 0x0010 /* Configuration base IO address */
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#define CBIO_MIO 0x00000001 /* Memory I/O. 1 = I/O. */
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#define CSR_SIZE 0x400 /* you can work this out by writing
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all F's to CBIO */
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/*****************************************************************************
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* Setup Frame, if needed *
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*****************************************************************************/
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#define SETUP_FRAME_NEEDED 1 /* Do we need a setup frame? */
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#define SETUP_FRAME_SIZE 192
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#define SETUP_PHYSICAL_ADDRESS_OFFSET 156
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#define SETUP_HASH_FILTER_SIZE 128
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/*****************************************************************************
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* Data Structures *
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*****************************************************************************/
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/*
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* TX descriptor. Must be longword aligned in memory.
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*/
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typedef struct {
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union {
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unsigned int tdes0;
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struct {
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unsigned int DE : 1; /* deferred */
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unsigned int UF : 1; /* underflow error */
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unsigned int LF : 1; /* link fail */
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unsigned int CC : 4; /* 6:3 Collision count */
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unsigned int HF : 1; /* Heartbeat fail */
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unsigned int EC : 1; /* excessive collisions */
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unsigned int LC : 1; /* late collisions */
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unsigned int NC : 1; /* no carrier */
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unsigned int LO : 1; /* loss of carrier */
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unsigned int unused_1 : 2; /* 13:12 */
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unsigned int TO : 1; /* transmit jabber timeout */
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unsigned int ES : 1; /* error summary */
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unsigned int unused_12 : 15;
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/* 30:16 */
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unsigned int OWN : 1; /* Own bit, 1 = 21040 */
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} s_tdes0;
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} u_tdes0;
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union {
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unsigned int tdes1;
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struct {
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unsigned int TBS1 : 11; /* 10:0 transmit buffer size 1 */
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unsigned int TBS2 : 11; /* 21:11 transmit buffer size 2 */
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unsigned int HP : 1; /* Hash/Perfect filtering */
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unsigned int DPD : 1; /* disable padding */
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unsigned int TCH : 1; /* Second address chained */
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unsigned int TER : 1; /* transmit end of ring */
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unsigned int AC : 1; /* add CRC disable */
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unsigned int SET : 1; /* setup packet */
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unsigned int IV : 1; /* inverse filtering */
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unsigned int FS : 1; /* First segment */
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unsigned int LS : 1; /* last segment */
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unsigned int IC : 1; /* interrupt on completion */
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} s_tdes1;
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} u_tdes1;
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unsigned int tdes2;
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unsigned int tdes3;
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} DECCHIP_21040_TX_BD;
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/*
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* Receive descriptor. Must be longword aligned in memory.
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*/
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typedef struct {
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union {
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unsigned int rdes0;
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struct {
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unsigned int OF : 1; /* overflow */
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unsigned int CE : 1; /* CRC error */
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unsigned int DB : 1; /* dribbling bit */
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unsigned int unused_1 : 1; /* 3 */
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unsigned int RJ : 1; /* Receive watchdog */
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unsigned int FT : 1; /* frame type */
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unsigned int CS : 1; /* collision seen */
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unsigned int TL : 1; /* frame too long */
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unsigned int LS : 1; /* last descriptor */
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unsigned int FS : 1; /* First descriptor */
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unsigned int MF : 1; /* Multicast frame */
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unsigned int RF : 1; /* runt frame */
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unsigned int DT : 2; /* 13:12 Data type */
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unsigned int LE : 1; /* length error */
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unsigned int ES : 1; /* error summary */
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unsigned int FL : 15; /* Frame Length */
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unsigned int OWN : 1; /* Own bit 1 = 21040 */
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} s_rdes0;
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} u_rdes0;
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union {
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unsigned int rdes1;
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struct {
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unsigned int RBS1 : 11; /* 10:0 Buffer Size 1 */
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unsigned int RBS2 : 11; /* 21:11 Buffer Size 2 */
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unsigned int unused_1 : 2; /* 23:22 */
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unsigned int RCH : 1; /* Second address chained */
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unsigned int RER : 1; /* Receive end of ring */
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unsigned int unused_2 : 6; /* 31:26 */
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} s_rdes1;
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} u_rdes1;
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unsigned int rdes2;
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unsigned int rdes3;
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} DECCHIP_21040_RX_BD;
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/*
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* Each device has a block of counters associated with it.
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*/
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typedef struct counters {
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/*
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* Transmit counters.
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*/
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unsigned int tx_restarted;
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unsigned int p_tx;
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unsigned int b_tx;
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unsigned int tx_err_UF;
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unsigned int tx_err_EC;
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unsigned int tx_err_LC;
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unsigned int tx_err_NC;
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unsigned int tx_err_LO;
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unsigned int tx_err_TO;
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unsigned int tx_err_LF;
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/*
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* Receive couters.
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*/
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unsigned int rx_restarted;
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unsigned int p_rx;
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unsigned int mf_rx;
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unsigned int b_rx;
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unsigned int rx_err_OF;
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unsigned int rx_err_CE;
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unsigned int rx_err_CS;
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unsigned int rx_err_TL;
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unsigned int rx_err_LE;
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unsigned int rx_err_RF;
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} counters_t;
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/*
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* Describe what a particular DECchip 21040 looks like.
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*/
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typedef struct DECchip_21040_device {
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unsigned int device; /* DBM device number */
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unsigned int index; /* Index into static structures */
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PCIDevice_t *pci; /* The PCI device */
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unsigned long PCI_IO_Base; /* Swizzled IO base address */
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unsigned int rx_index; /* Next RX buffer */
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unsigned int tx_index; /* Next TX buffer */
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struct counters *counters; /* block of counter information */
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mac_addr hw_address; /* This device's h/w address */
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char *setup_frame; /* setup frame */
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struct {
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unsigned int exists : 1; /* Does this device exist? */
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unsigned int allocated : 1; /* Is this device in use? */
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unsigned int initialised : 1; /* Has the device been initialised? */
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unsigned int loopback : 1; /* loopback mode selected */
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unsigned int setup_frame : 1; /* setup frame needed? */
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unsigned int hw_valid : 1; /* Is the hardware address valid? */
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} flags;
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} DECchip_21040_device_t;
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/* /ether/DEC21040.c */
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extern DECchip_21040_device_t * DECchip_21040_device_find(int device_no);
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extern int DECchip_21040_device_register(int device_no);
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extern void DECchip_21040_device_init_module(void );
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#endif /* NEEDPCI */
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#endif /* __DECCHIP21040_H_LOADED */
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