540 lines
16 KiB
C++
540 lines
16 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#include "arch/sparc/miscregfile.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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using namespace SparcISA;
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using namespace std;
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class Checkpoint;
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//These functions map register indices to names
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string SparcISA::getMiscRegName(RegIndex index)
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{
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static::string miscRegName[NumMiscRegs] =
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{"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
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"gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
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"stick", "stick_cmpr",
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"tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
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"pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
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"wstate", "gl",
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"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
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"hstick_cmpr",
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"fsr"};
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return miscRegName[index];
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}
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#if FULL_SYSTEM
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//XXX These need an implementation someplace
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/** Fullsystem only register version of ReadRegWithEffect() */
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MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
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/** Fullsystem only register version of SetRegWithEffect() */
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Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext * tc);
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#endif
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void MiscRegFile::reset()
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{
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pstateFields.pef = 0; //No FPU
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//pstateFields.pef = 1; //FPU
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#if FULL_SYSTEM
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//For SPARC, when a system is first started, there is a power
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//on reset Trap which sets the processor into the following state.
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//Bits that aren't set aren't defined on startup.
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tl = MaxTL;
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gl = MaxGL;
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tickFields.counter = 0; //The TICK register is unreadable bya
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tickFields.npt = 1; //The TICK register is unreadable by by !priv
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softint = 0; // Clear all the soft interrupt bits
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tick_cmprFields.int_dis = 1; // disable timer compare interrupts
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tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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stickFields.npt = 1; //The TICK register is unreadable by by !priv
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stick_cmprFields.int_dis = 1; // disable timer compare interrupts
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stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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tt[tl] = power_on_reset;
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pstate = 0; // fields 0 but pef
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pstateFields.pef = 1;
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hpstate = 0;
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hpstateFields.red = 1;
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hpstateFields.hpriv = 1;
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hpstateFields.tlz = 0; // this is a guess
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hintp = 0; // no interrupts pending
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hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
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hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
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#else
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/* //This sets up the initial state of the processor for usermode processes
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pstateFields.priv = 0; //Process runs in user mode
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pstateFields.ie = 1; //Interrupts are enabled
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fsrFields.rd = 0; //Round to nearest
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fsrFields.tem = 0; //Floating point traps not enabled
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fsrFields.ns = 0; //Non standard mode off
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fsrFields.qne = 0; //Floating point queue is empty
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fsrFields.aexc = 0; //No accrued exceptions
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fsrFields.cexc = 0; //No current exceptions
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//Register window management registers
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otherwin = 0; //No windows contain info from other programs
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canrestore = 0; //There are no windows to pop
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cansave = MaxTL - 2; //All windows are available to save into
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cleanwin = MaxTL;*/
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#endif
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}
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MiscReg MiscRegFile::readReg(int miscReg)
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{
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switch (miscReg) {
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case MISCREG_Y:
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return y;
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case MISCREG_CCR:
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return ccr;
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case MISCREG_ASI:
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return asi;
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case MISCREG_FPRS:
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return fprs;
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case MISCREG_TICK:
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return tick;
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("ASR number %d not implemented\n", miscReg - AsrStart);
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case MISCREG_GSR:
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return gsr;
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case MISCREG_SOFTINT:
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return softint;
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case MISCREG_TICK_CMPR:
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return tick_cmpr;
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case MISCREG_STICK:
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return stick;
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case MISCREG_STICK_CMPR:
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return stick_cmpr;
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/** Privilged Registers */
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case MISCREG_TPC:
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return tpc[tl-1];
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case MISCREG_TNPC:
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return tnpc[tl-1];
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case MISCREG_TSTATE:
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return tstate[tl-1];
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case MISCREG_TT:
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return tt[tl-1];
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick registers not implemented\n");
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case MISCREG_TBA:
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return tba;
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case MISCREG_PSTATE:
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return pstate;
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case MISCREG_TL:
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return tl;
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case MISCREG_PIL:
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return pil;
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case MISCREG_CWP:
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return cwp;
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case MISCREG_CANSAVE:
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return cansave;
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case MISCREG_CANRESTORE:
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return canrestore;
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case MISCREG_CLEANWIN:
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return cleanwin;
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case MISCREG_OTHERWIN:
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return otherwin;
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case MISCREG_WSTATE:
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return wstate;
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case MISCREG_GL:
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return gl;
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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return hpstate;
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case MISCREG_HTSTATE:
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return htstate[tl-1];
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case MISCREG_HINTP:
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panic("HINTP not implemented\n");
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case MISCREG_HTBA:
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return htba;
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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case MISCREG_STRAND_STS_REG:
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return strandStatusReg;
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case MISCREG_HSTICK_CMPR:
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return hstick_cmpr;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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return fsr;
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default:
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panic("Miscellaneous register %d not implemented\n", miscReg);
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}
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}
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MiscReg MiscRegFile::readRegWithEffect(int miscReg,
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Fault &fault, ThreadContext * tc)
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{
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fault = NoFault;
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switch (miscReg) {
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case MISCREG_Y:
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case MISCREG_CCR:
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case MISCREG_ASI:
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return readReg(miscReg);
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case MISCREG_TICK:
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case MISCREG_PRIVTICK:
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// Check for reading privilege
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if (tickFields.npt && !isNonPriv()) {
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fault = new PrivilegedAction;
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return 0;
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}
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return tc->getCpuPtr()->curCycle() - tickFields.counter |
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tickFields.npt << 63;
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case MISCREG_PC:
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return tc->readPC();
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case MISCREG_FPRS:
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fault = new UnimpFault("FPU not implemented\n");
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return 0;
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case MISCREG_PCR:
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fault = new UnimpFault("Performance Instrumentation not impl\n");
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return 0;
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case MISCREG_PIC:
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fault = new UnimpFault("Performance Instrumentation not impl\n");
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return 0;
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case MISCREG_GSR:
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return readReg(miscReg);
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/** Privilged Registers */
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case MISCREG_TPC:
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case MISCREG_TNPC:
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case MISCREG_TSTATE:
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case MISCREG_TT:
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if (tl == 0) {
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fault = new IllegalInstruction;
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return 0;
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} // NOTE THE FALL THROUGH!
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case MISCREG_PSTATE:
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case MISCREG_TL:
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return readReg(miscReg);
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case MISCREG_TBA:
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return readReg(miscReg) & ULL(~0x7FFF);
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case MISCREG_PIL:
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case MISCREG_CWP:
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case MISCREG_CANSAVE:
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case MISCREG_CANRESTORE:
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case MISCREG_CLEANWIN:
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case MISCREG_OTHERWIN:
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case MISCREG_WSTATE:
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case MISCREG_GL:
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return readReg(miscReg);
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/** Floating Point Status Register */
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case MISCREG_FSR:
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panic("Floating Point not implemented\n");
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default:
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#if FULL_SYSTEM
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return readFSRegWithEffect(miscReg, fault, tc);
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#else
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fault = new IllegalInstruction;
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return 0;
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#endif
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}
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}
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Fault MiscRegFile::setReg(int miscReg, const MiscReg &val)
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{
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switch (miscReg) {
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case MISCREG_Y:
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y = val;
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return NoFault;
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case MISCREG_CCR:
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ccr = val;
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return NoFault;
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case MISCREG_ASI:
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asi = val;
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return NoFault;
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case MISCREG_FPRS:
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fprs = val;
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return NoFault;
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case MISCREG_TICK:
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tick = val;
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return NoFault;
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case MISCREG_PCR:
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case MISCREG_PIC:
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panic("ASR number %d not implemented\n", miscReg - AsrStart);
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case MISCREG_GSR:
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gsr = val;
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case MISCREG_SOFTINT:
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softint = val;
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return NoFault;
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case MISCREG_TICK_CMPR:
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tick_cmpr = val;
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return NoFault;
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case MISCREG_STICK:
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stick = val;
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return NoFault;
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case MISCREG_STICK_CMPR:
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stick_cmpr = val;
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return NoFault;
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/** Privilged Registers */
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case MISCREG_TPC:
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tpc[tl-1] = val;
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return NoFault;
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case MISCREG_TNPC:
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tnpc[tl-1] = val;
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return NoFault;
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case MISCREG_TSTATE:
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tstate[tl-1] = val;
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return NoFault;
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case MISCREG_TT:
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tt[tl-1] = val;
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return NoFault;
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case MISCREG_PRIVTICK:
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panic("Priviliged access to tick regesiters not implemented\n");
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case MISCREG_TBA:
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tba = val;
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return NoFault;
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case MISCREG_PSTATE:
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pstate = val;
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return NoFault;
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case MISCREG_TL:
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tl = val;
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return NoFault;
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case MISCREG_PIL:
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pil = val;
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return NoFault;
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case MISCREG_CWP:
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cwp = val;
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return NoFault;
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case MISCREG_CANSAVE:
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cansave = val;
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return NoFault;
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case MISCREG_CANRESTORE:
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canrestore = val;
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return NoFault;
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case MISCREG_CLEANWIN:
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cleanwin = val;
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return NoFault;
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case MISCREG_OTHERWIN:
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otherwin = val;
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return NoFault;
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case MISCREG_WSTATE:
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wstate = val;
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return NoFault;
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case MISCREG_GL:
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gl = val;
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return NoFault;
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/** Hyper privileged registers */
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case MISCREG_HPSTATE:
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hpstate = val;
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return NoFault;
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case MISCREG_HTSTATE:
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htstate[tl-1] = val;
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return NoFault;
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case MISCREG_HINTP:
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panic("HINTP not implemented\n");
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case MISCREG_HTBA:
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htba = val;
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return NoFault;
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case MISCREG_STRAND_STS_REG:
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strandStatusReg = val;
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return NoFault;
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case MISCREG_HSTICK_CMPR:
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hstick_cmpr = val;
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return NoFault;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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fsr = val;
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return NoFault;
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default:
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panic("Miscellaneous register %d not implemented\n", miscReg);
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}
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}
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Fault MiscRegFile::setRegWithEffect(int miscReg,
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const MiscReg &val, ThreadContext * tc)
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{
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const uint64_t Bit64 = (1ULL << 63);
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switch (miscReg) {
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case MISCREG_Y:
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case MISCREG_CCR:
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case MISCREG_ASI:
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setReg(miscReg, val);
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return NoFault;
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case MISCREG_PRIVTICK:
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case MISCREG_TICK:
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if (isNonPriv())
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return new PrivilegedOpcode;
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if (isPriv())
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return new PrivilegedAction;
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tickFields.counter = tc->getCpuPtr()->curCycle() - val & ~Bit64;
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tickFields.npt = val & Bit64 ? 1 : 0;
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return NoFault;
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case MISCREG_PC:
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return new IllegalInstruction;
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case MISCREG_FPRS:
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return new UnimpFault("FPU not implemented\n");
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case MISCREG_PCR:
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return new UnimpFault("Performance Instrumentation not impl\n");
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case MISCREG_PIC:
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return new UnimpFault("Performance Instrumentation not impl\n");
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case MISCREG_GSR:
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return setReg(miscReg, val);
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/** Privilged Registers */
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case MISCREG_TPC:
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case MISCREG_TNPC:
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case MISCREG_TSTATE:
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case MISCREG_TT:
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if (tl == 0)
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return new IllegalInstruction;
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setReg(miscReg, val);
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return NoFault;
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case MISCREG_TBA:
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// clear lower 7 bits on writes.
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setReg(miscReg, val & ULL(~0x7FFF));
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return NoFault;
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case MISCREG_PSTATE:
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setReg(miscReg, val);
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return NoFault;
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case MISCREG_TL:
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if (isHyperPriv() && val > MaxTL)
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setReg(miscReg, MaxTL);
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else if (isPriv() && !isHyperPriv() && val > MaxPTL)
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setReg(miscReg, MaxPTL);
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else
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setReg(miscReg, val);
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return NoFault;
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case MISCREG_CWP:
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tc->changeRegFileContext(CONTEXT_CWP, val);
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case MISCREG_CANSAVE:
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case MISCREG_CANRESTORE:
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case MISCREG_CLEANWIN:
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case MISCREG_OTHERWIN:
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case MISCREG_WSTATE:
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setReg(miscReg, val);
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return NoFault;
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case MISCREG_GL:
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int newval;
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if (isHyperPriv() && val > MaxGL)
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newval = MaxGL;
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else if (isPriv() && !isHyperPriv() && val > MaxPGL)
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newval = MaxPGL;
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else
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newval = val;
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tc->changeRegFileContext(CONTEXT_GLOBALS, newval);
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setReg(miscReg, newval);
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return NoFault;
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/** Floating Point Status Register */
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case MISCREG_FSR:
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setReg(miscReg, val);
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default:
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#if FULL_SYSTEM
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setFSRegWithEffect(miscReg, val, tc);
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#else
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return new IllegalInstruction;
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#endif
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}
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}
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void MiscRegFile::serialize(std::ostream & os)
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{
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SERIALIZE_SCALAR(pstate);
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SERIALIZE_SCALAR(tba);
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SERIALIZE_SCALAR(y);
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SERIALIZE_SCALAR(pil);
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SERIALIZE_SCALAR(gl);
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SERIALIZE_SCALAR(cwp);
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SERIALIZE_ARRAY(tt, MaxTL);
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SERIALIZE_SCALAR(ccr);
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SERIALIZE_SCALAR(asi);
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SERIALIZE_SCALAR(tl);
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SERIALIZE_ARRAY(tpc, MaxTL);
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SERIALIZE_ARRAY(tnpc, MaxTL);
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SERIALIZE_ARRAY(tstate, MaxTL);
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SERIALIZE_SCALAR(tick);
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SERIALIZE_SCALAR(cansave);
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SERIALIZE_SCALAR(canrestore);
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SERIALIZE_SCALAR(otherwin);
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SERIALIZE_SCALAR(cleanwin);
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SERIALIZE_SCALAR(wstate);
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SERIALIZE_SCALAR(fsr);
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SERIALIZE_SCALAR(fprs);
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SERIALIZE_SCALAR(hpstate);
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SERIALIZE_ARRAY(htstate, MaxTL);
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SERIALIZE_SCALAR(htba);
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SERIALIZE_SCALAR(hstick_cmpr);
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}
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|
|
|
void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
|
|
{
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|
UNSERIALIZE_SCALAR(pstate);
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|
UNSERIALIZE_SCALAR(tba);
|
|
UNSERIALIZE_SCALAR(y);
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|
UNSERIALIZE_SCALAR(pil);
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|
UNSERIALIZE_SCALAR(gl);
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|
UNSERIALIZE_SCALAR(cwp);
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|
UNSERIALIZE_ARRAY(tt, MaxTL);
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|
UNSERIALIZE_SCALAR(ccr);
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|
UNSERIALIZE_SCALAR(asi);
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|
UNSERIALIZE_SCALAR(tl);
|
|
UNSERIALIZE_ARRAY(tpc, MaxTL);
|
|
UNSERIALIZE_ARRAY(tnpc, MaxTL);
|
|
UNSERIALIZE_ARRAY(tstate, MaxTL);
|
|
UNSERIALIZE_SCALAR(tick);
|
|
UNSERIALIZE_SCALAR(cansave);
|
|
UNSERIALIZE_SCALAR(canrestore);
|
|
UNSERIALIZE_SCALAR(otherwin);
|
|
UNSERIALIZE_SCALAR(cleanwin);
|
|
UNSERIALIZE_SCALAR(wstate);
|
|
UNSERIALIZE_SCALAR(fsr);
|
|
UNSERIALIZE_SCALAR(fprs);
|
|
UNSERIALIZE_SCALAR(hpstate);
|
|
UNSERIALIZE_ARRAY(htstate, MaxTL);
|
|
UNSERIALIZE_SCALAR(htba);
|
|
UNSERIALIZE_SCALAR(hstick_cmpr);
|
|
}
|
|
|