gem5/src/mem/cache/prefetch
Andreas Hansson 362160c8ae mem: Add deferred packet class to prefetcher
This patch removes the time field from the packet as it was only used
by the preftecher. Similar to the packet queue, the prefetcher now
wraps the packet in a deferred packet, which also has a tick
representing the absolute time when the packet should be sent.
2013-02-19 05:56:06 -05:00
..
base.cc mem: Add deferred packet class to prefetcher 2013-02-19 05:56:06 -05:00
base.hh mem: Add deferred packet class to prefetcher 2013-02-19 05:56:06 -05:00
ghb.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
ghb.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
Prefetcher.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
SConscript prefetcher: Make prefetcher a sim object instead of it being a parameter on cache 2012-02-12 16:07:38 -06:00
stride.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
stride.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
tagged.cc Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00
tagged.hh Mem: Use cycles to express cache-related latencies 2012-10-15 08:10:54 -04:00