73 lines
2.4 KiB
Plaintext
73 lines
2.4 KiB
Plaintext
// Copyright (c) 2006 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Ali Saidi
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// Gabe Black
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// Steve Reinhardt
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////////////////////////////////////////////////////////////////////
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//
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// Output include file directives.
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//
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output header {{
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#include <sstream>
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#include <iostream>
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#include "cpu/static_inst.hh"
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#include "arch/sparc/faults.hh"
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#include "mem/request.hh" // some constructors use MemReq flags
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#include "mem/packet.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/regfile.hh"
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}};
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output decoder {{
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#include "base/cprintf.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/thread_context.hh" // for Jump::branchTarget()
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#if defined(linux)
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#include <fenv.h>
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#endif
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using namespace SparcISA;
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}};
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output exec {{
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#if defined(linux)
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#include <fenv.h>
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#endif
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#include "arch/sparc/asi.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "sim/sim_exit.hh"
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using namespace SparcISA;
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}};
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