172 lines
8.6 KiB
C++
Executable file
172 lines
8.6 KiB
C++
Executable file
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Brett Miller
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*/
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#ifndef __ARCH_MIPS_DSP_HH__
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#define __ARCH_MIPS_DSP_HH__
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#include "arch/mips/types.hh"
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#include "arch/mips/isa_traits.hh"
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#include "base/misc.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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class ThreadContext;
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namespace MipsISA {
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// SIMD formats
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enum {
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SIMD_FMT_L, // long word
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SIMD_FMT_W, // word
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SIMD_FMT_PH, // paired halfword
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SIMD_FMT_QB, // quad byte
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SIMD_NUM_FMTS
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};
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// DSPControl Fields
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enum {
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DSP_POS, // insertion bitfield position
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DSP_SCOUNT, // insertion bitfield size
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DSP_C, // carry bit
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DSP_OUFLAG, // overflow-underflow flag
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DSP_CCOND, // condition code
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DSP_EFI, // extract fail indicator bit
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DSP_NUM_FIELDS
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};
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// compare instruction operations
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enum {
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CMP_EQ, // equal
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CMP_LT, // less than
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CMP_LE // less than or equal
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};
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// SIMD operation order modes
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enum {
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MODE_L, // left
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MODE_R, // right
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MODE_LA, // left-alternate
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MODE_RA, // right-alternate
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MODE_X // cross
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};
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// dsp operation parameters
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enum { UNSIGNED, SIGNED };
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enum { NOSATURATE, SATURATE };
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enum { NOROUND, ROUND };
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// DSPControl field positions and masks
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const uint32_t DSP_CTL_POS[DSP_NUM_FIELDS] = { 0, 7, 13, 16, 24, 14 };
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const uint32_t DSP_CTL_MASK[DSP_NUM_FIELDS] = { 0x0000003f, 0x00001f80, 0x00002000,
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0x00ff0000, 0x0f000000, 0x00004000 };
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// SIMD format constants
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const uint32_t SIMD_MAX_VALS = 4; // maximum values per register
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const uint32_t SIMD_NVALS[SIMD_NUM_FMTS] = { 1, 1, 2, 4 }; // number of values in fmt
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const uint32_t SIMD_NBITS[SIMD_NUM_FMTS] = { 64, 32, 16, 8 }; // number of bits per value
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const uint32_t SIMD_LOG2N[SIMD_NUM_FMTS] = { 6, 5, 4, 3 }; // log2( bits per value )
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// DSP maximum values
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const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
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const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
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const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
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const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
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const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
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const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
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const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
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const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
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const uint64_t FIXED_SMAX[SIMD_NUM_FMTS] = { FIXED_L_SMAX, FIXED_W_SMAX, FIXED_H_SMAX, FIXED_B_SMAX };
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const uint64_t FIXED_UMAX[SIMD_NUM_FMTS] = { FIXED_L_UMAX, FIXED_W_UMAX, FIXED_H_UMAX, FIXED_B_UMAX };
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// DSP minimum values
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const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
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const uint64_t FIXED_W_SMIN = ULL(0xffffffff80000000);
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const uint64_t FIXED_H_SMIN = ULL(0xffffffffffff8000);
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const uint64_t FIXED_B_SMIN = ULL(0xffffffffffffff80);
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const uint64_t FIXED_L_UMIN = ULL(0x0000000000000000);
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const uint64_t FIXED_W_UMIN = ULL(0x0000000000000000);
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const uint64_t FIXED_H_UMIN = ULL(0x0000000000000000);
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const uint64_t FIXED_B_UMIN = ULL(0x0000000000000000);
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const uint64_t FIXED_SMIN[SIMD_NUM_FMTS] = { FIXED_L_SMIN, FIXED_W_SMIN, FIXED_H_SMIN, FIXED_B_SMIN };
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const uint64_t FIXED_UMIN[SIMD_NUM_FMTS] = { FIXED_L_UMIN, FIXED_W_UMIN, FIXED_H_UMIN, FIXED_B_UMIN };
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// DSP utility functions
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int32_t bitrev( int32_t value );
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uint64_t dspSaturate( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
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uint64_t checkOverflow( uint64_t value, int32_t fmt, int32_t sign, uint32_t *overflow );
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uint64_t signExtend( uint64_t value, int32_t signpos );
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uint64_t addHalfLsb( uint64_t value, int32_t lsbpos );
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int32_t dspAbs( int32_t a, int32_t fmt, uint32_t *dspctl );
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int32_t dspAdd( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
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int32_t dspAddh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
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int32_t dspSub( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
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int32_t dspSubh( int32_t a, int32_t b, int32_t fmt, int32_t round, int32_t sign );
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int32_t dspShll( int32_t a, uint32_t sa, int32_t fmt, int32_t saturate, int32_t sign, uint32_t *dspctl );
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int32_t dspShrl( int32_t a, uint32_t sa, int32_t fmt, int32_t sign );
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int32_t dspShra( int32_t a, uint32_t sa, int32_t fmt, int32_t round, int32_t sign, uint32_t *dspctl );
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int32_t dspMul( int32_t a, int32_t b, int32_t fmt, int32_t saturate, uint32_t *dspctl );
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int32_t dspMulq( int32_t a, int32_t b, int32_t fmt, int32_t saturate, int32_t round, uint32_t *dspctl );
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int32_t dspMuleu( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
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int32_t dspMuleq( int32_t a, int32_t b, int32_t mode, uint32_t *dspctl );
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int64_t dspDpaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
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int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
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int64_t dspDpsq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t infmt,
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int32_t outfmt, int32_t postsat, int32_t mode, uint32_t *dspctl );
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int64_t dspDpa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
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int64_t dspDps( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, int32_t sign, int32_t mode );
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int64_t dspMaq( int64_t dspac, int32_t a, int32_t b, int32_t ac,
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int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl );
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int64_t dspMulsa( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt );
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int64_t dspMulsaq( int64_t dspac, int32_t a, int32_t b, int32_t ac, int32_t fmt, uint32_t *dspctl );
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void dspCmp( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
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int32_t dspCmpg( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op );
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int32_t dspCmpgd( int32_t a, int32_t b, int32_t fmt, int32_t sign, int32_t op, uint32_t *dspctl );
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int32_t dspPrece( int32_t a, int32_t infmt, int32_t insign, int32_t outfmt, int32_t outsign, int32_t mode );
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int32_t dspPrecrqu( int32_t a, int32_t b, uint32_t *dspctl );
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int32_t dspPrecrq( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
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int32_t dspPrecrSra( int32_t a, int32_t b, int32_t sa, int32_t fmt, int32_t round );
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int32_t dspPick( int32_t a, int32_t b, int32_t fmt, uint32_t *dspctl );
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int32_t dspPack( int32_t a, int32_t b, int32_t fmt );
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int32_t dspExtr( int64_t dspac, int32_t fmt, int32_t sa, int32_t round,
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int32_t saturate, uint32_t *dspctl );
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int32_t dspExtp( int64_t dspac, int32_t size, uint32_t *dspctl );
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int32_t dspExtpd( int64_t dspac, int32_t size, uint32_t *dspctl );
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// SIMD pack/unpack utility functions
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void simdPack( uint64_t *values_ptr, int32_t *reg, int32_t fmt );
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void simdUnpack( int32_t reg, uint64_t *values_ptr, int32_t fmt, int32_t sign );
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// DSPControl r/w utility functions
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void writeDSPControl( uint32_t *dspctl, uint32_t value, uint32_t mask );
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uint32_t readDSPControl( uint32_t *dspctl, uint32_t mask );
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};
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#endif
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