3923eec0ef
Should enable implementation of split-phase timing loads
with new memory model.
May create slight timing differences under FullCPU, as I
believe we were not handling software prefetches correctly
before when the split MemAcc/Exec model was used. I haven't
looked into this in any detail though.
arch/alpha/isa/decoder.isa:
HwLoadStore format split into separate HwLoad and
HwStore formats.
Copy instructions now fall under MiscPrefetch format.
Mem_write_result is now just write_result in store
conditionals.
arch/alpha/isa/mem.isa:
Split MemAccExecute and LoadStoreExecute templates
into separate templates for loads and stores; now
that memory operands are handled differently from
registers, it's impossible to have a single template
serve both.
Also unified the handling of "regular" prefetches
(loads to r31) and "misc" prefetches (e.g., wh64)
under the new scheme. It looks like SW prefetches
were not handled correctly in FullCPU up til now,
since we generated an execute() method for the outer
instruction but didn't generate a proper method for
MemAcc::execute() (instead getting a default no-op
method for that).
arch/alpha/isa/pal.isa:
Split HwLoadStore into separate HwLoad and HwStore
formats to select proper template (see change to
mem.isa in this changeset).
arch/isa_parser.py:
Stop trying to treat memory operands like register
operands, since we never used them in a uniform way
anyway, and it made it impossible to do split-phase
loads as needed for the new CPU model. Now there's no
more 'op_mem_rd', 'op_nonmem_rd', etc.: 'op_rd' just does
register operands, and the template code is responsible
for formulating the call to the memory system. Right now
the only thing exported by InstObjParams is a new attribute
'mem_acc_size' which gives the memory access size in bits,
though more attributes can be added if needed.
Also moved code in findOperands() method to
OperandDescriptorList.__init__(), which is where it belongs.
--HG--
extra : convert_revision : 6d53d07e0c5e828455834ded4395fa40f9146a34
525 lines
16 KiB
C++
525 lines
16 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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/**
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* Base class for general Alpha memory-format instructions.
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*/
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class Memory : public AlphaStaticInst
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{
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protected:
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/// Memory request flags. See mem_req_base.hh.
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unsigned memAccessFlags;
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/// Pointer to EAComp object.
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const StaticInstPtr<AlphaISA> eaCompPtr;
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/// Pointer to MemAcc object.
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const StaticInstPtr<AlphaISA> memAccPtr;
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/// Constructor
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Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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public:
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const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
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const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
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};
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/**
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* Base class for memory-format instructions using a 32-bit
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* displacement (i.e. most of them).
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*/
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class MemoryDisp32 : public Memory
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{
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protected:
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/// Displacement for EA calculation (signed).
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int32_t disp;
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/// Constructor.
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MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
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disp(MEMDISP)
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{
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}
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};
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/**
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* Base class for a few miscellaneous memory-format insts
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* that don't interpret the disp field: wh64, fetch, fetch_m, ecb.
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* None of these instructions has a destination register either.
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*/
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class MemoryNoDisp : public Memory
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{
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protected:
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/// Constructor
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MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
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StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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Memory::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %c%d,%d(r%d)", mnemonic,
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flags[IsFloating] ? 'f' : 'r', RA, MEMDISP, RB);
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}
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std::string
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MemoryNoDisp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s (r%d)", mnemonic, RB);
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}
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}};
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def format LoadAddress(code) {{
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iop = InstObjParams(name, Name, 'MemoryDisp32', CodeBlock(code))
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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def template LoadStoreDeclare {{
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/**
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* Static instruction class for "%(mnemonic)s".
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*/
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class %(class_name)s : public %(base_class)s
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{
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protected:
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/**
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* "Fake" effective address computation class for "%(mnemonic)s".
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*/
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class EAComp : public %(base_class)s
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{
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public:
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/// Constructor
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EAComp(MachInst machInst);
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%(BasicExecDeclare)s
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};
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/**
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* "Fake" memory access instruction class for "%(mnemonic)s".
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*/
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class MemAcc : public %(base_class)s
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{
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public:
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/// Constructor
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MemAcc(MachInst machInst);
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%(BasicExecDeclare)s
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};
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public:
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/// Constructor.
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%(class_name)s(MachInst machInst);
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%(BasicExecDeclare)s
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};
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}};
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def template LoadStoreConstructor {{
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/** TODO: change op_class to AddrGenOp or something (requires
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* creating new member of OpClass enum in op_class.hh, updating
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* config files, etc.). */
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inline %(class_name)s::EAComp::EAComp(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (EAComp)", machInst, IntAluOp)
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{
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%(ea_constructor)s;
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}
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inline %(class_name)s::MemAcc::MemAcc(MachInst machInst)
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: %(base_class)s("%(mnemonic)s (MemAcc)", machInst, %(op_class)s)
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{
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%(memacc_constructor)s;
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}
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inline %(class_name)s::%(class_name)s(MachInst machInst)
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: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
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new EAComp(machInst), new MemAcc(machInst))
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{
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%(constructor)s;
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}
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}};
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def template EACompExecute {{
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Fault
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%(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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if (fault == No_Fault) {
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%(op_wb)s;
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xc->setEA(EA);
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}
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return fault;
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}
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}};
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def template LoadMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == No_Fault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(code)s;
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}
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if (fault == No_Fault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template LoadExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == No_Fault) {
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fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
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%(memacc_code)s;
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}
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if (fault == No_Fault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreMemAccExecute {{
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Fault
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%(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == No_Fault) {
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%(code)s;
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}
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if (fault == No_Fault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == No_Fault) {
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%(postacc_code)s;
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}
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if (fault == No_Fault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template StoreExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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uint64_t write_result = 0;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == No_Fault) {
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%(memacc_code)s;
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}
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if (fault == No_Fault) {
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fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
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memAccessFlags, &write_result);
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if (traceData) { traceData->setData(Mem); }
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}
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if (fault == No_Fault) {
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%(postacc_code)s;
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}
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if (fault == No_Fault) {
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%(op_wb)s;
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}
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return fault;
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}
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}};
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def template MiscMemAccExecute {{
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Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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EA = xc->getEA();
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if (fault == No_Fault) {
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%(code)s;
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}
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return No_Fault;
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}
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}};
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def template MiscExecute {{
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Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
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Trace::InstRecord *traceData) const
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{
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Addr EA;
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Fault fault = No_Fault;
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%(fp_enable_check)s;
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%(op_decl)s;
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%(op_rd)s;
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%(ea_code)s;
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if (fault == No_Fault) {
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%(memacc_code)s;
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}
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return No_Fault;
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}
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}};
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// load instructions use Ra as dest, so check for
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// Ra == 31 to detect nops
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def template LoadNopCheckDecode {{
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{
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AlphaStaticInst *i = new %(class_name)s(machInst);
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if (RA == 31) {
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i = makeNop(i);
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}
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return i;
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}
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}};
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// for some load instructions, Ra == 31 indicates a prefetch (not a nop)
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def template LoadPrefetchCheckDecode {{
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{
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if (RA != 31) {
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return new %(class_name)s(machInst);
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}
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else {
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return new %(class_name)sPrefetch(machInst);
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}
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}
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}};
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let {{
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def LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code = '',
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base_class = 'MemoryDisp32', flags = [],
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decode_template = BasicDecode, exec_template_base = ''):
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# Segregate flags into instruction flags (handled by InstObjParams)
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# and memory access flags (handled here).
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# Would be nice to autogenerate this list, but oh well.
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valid_mem_flags = ['LOCKED', 'NO_FAULT', 'EVICT_NEXT', 'PF_EXCLUSIVE']
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mem_flags = [f for f in flags if f in valid_mem_flags]
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inst_flags = [f for f in flags if f not in valid_mem_flags]
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# add hook to get effective addresses into execution trace output.
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ea_code += '\nif (traceData) { traceData->setAddr(EA); }\n'
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# generate code block objects
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ea_cblk = CodeBlock(ea_code)
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memacc_cblk = CodeBlock(memacc_code)
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postacc_cblk = CodeBlock(postacc_code)
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# Some CPU models execute the memory operation as an atomic unit,
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# while others want to separate them into an effective address
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# computation and a memory access operation. As a result, we need
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# to generate three StaticInst objects. Note that the latter two
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# are nested inside the larger "atomic" one.
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# generate InstObjParams for EAComp object
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ea_iop = InstObjParams(name, Name, base_class, ea_cblk, inst_flags)
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# generate InstObjParams for MemAcc object
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memacc_iop = InstObjParams(name, Name, base_class, memacc_cblk, inst_flags)
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# in the split execution model, the MemAcc portion is responsible
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# for the post-access code.
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memacc_iop.postacc_code = postacc_cblk.code
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# generate InstObjParams for unified execution
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cblk = CodeBlock(ea_code + memacc_code + postacc_code)
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iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
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iop.ea_constructor = ea_cblk.constructor
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iop.ea_code = ea_cblk.code
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iop.memacc_constructor = memacc_cblk.constructor
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iop.memacc_code = memacc_cblk.code
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iop.postacc_code = postacc_cblk.code
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if mem_flags:
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s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
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iop.constructor += s
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memacc_iop.constructor += s
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# select templates
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memAccExecTemplate = eval(exec_template_base + 'MemAccExecute')
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fullExecTemplate = eval(exec_template_base + 'Execute')
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# (header_output, decoder_output, decode_block, exec_output)
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return (LoadStoreDeclare.subst(iop), LoadStoreConstructor.subst(iop),
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decode_template.subst(iop),
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EACompExecute.subst(ea_iop)
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+ memAccExecTemplate.subst(memacc_iop)
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+ fullExecTemplate.subst(iop))
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}};
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def format LoadOrNop(ea_code, memacc_code, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
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decode_template = LoadNopCheckDecode,
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exec_template_base = 'Load')
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}};
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// Note that the flags passed in apply only to the prefetch version
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def format LoadOrPrefetch(ea_code, memacc_code, *pf_flags) {{
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# declare the load instruction object and generate the decode block
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code,
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decode_template = LoadPrefetchCheckDecode,
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exec_template_base = 'Load')
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# Declare the prefetch instruction object.
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# convert flags from tuple to list to make them mutable
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pf_flags = list(pf_flags) + ['IsMemRef', 'IsLoad', 'IsDataPrefetch', 'MemReadOp', 'NO_FAULT']
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(pf_header_output, pf_decoder_output, _, pf_exec_output) = \
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LoadStoreBase(name, Name + 'Prefetch', ea_code,
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'xc->prefetch(EA, memAccessFlags);',
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flags = pf_flags, exec_template_base = 'Misc')
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header_output += pf_header_output
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decoder_output += pf_decoder_output
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exec_output += pf_exec_output
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}};
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def format Store(ea_code, memacc_code, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
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exec_template_base = 'Store')
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}};
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def format StoreCond(ea_code, memacc_code, postacc_code, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, postacc_code,
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flags = flags, exec_template_base = 'Store')
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}};
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// Use 'MemoryNoDisp' as base: for wh64, fetch, ecb
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def format MiscPrefetch(ea_code, memacc_code, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name, ea_code, memacc_code, flags = flags,
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base_class = 'MemoryNoDisp', exec_template_base = 'Misc')
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}};
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