162 lines
4.1 KiB
C++
162 lines
4.1 KiB
C++
/* $Id$ */
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/* @file
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* PCI Configspace implementation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/scsi_ctrl.hh"
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#include "dev/pciconfigall.hh"
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#include "dev/pcidev.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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PCIConfigAll::PCIConfigAll(const string &name, Tsunami *t,
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), tsunami(t)
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{
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//Put back pointer in tsunami
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tsunami->pciconfig = this;
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// Make all the pointers to devices null
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for(int x=0; x < MAX_PCI_DEV; x++)
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for(int y=0; y < MAX_PCI_FUNC; y++)
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devices[x][y] = NULL;
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}
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Fault
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PCIConfigAll::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(PCIConfigAll, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr & addr_mask);
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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if (devices[device][func] == NULL) {
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switch (req->size) {
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// case sizeof(uint64_t):
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// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
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// return No_Fault;
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case sizeof(uint32_t):
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*(uint32_t*)data = 0xFFFFFFFF;
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return No_Fault;
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case sizeof(uint16_t):
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*(uint16_t*)data = 0xFFFF;
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return No_Fault;
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case sizeof(uint8_t):
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*(uint8_t*)data = 0xFF;
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return No_Fault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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} else {
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switch (req->size) {
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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devices[device][func]->ReadConfig(reg, req->size, data);
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return No_Fault;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTFN("Tsunami PCI Configspace ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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PCIConfigAll::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = (req->paddr & addr_mask);
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int device = (daddr >> 11) & 0x1F;
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int func = (daddr >> 8) & 0x7;
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int reg = daddr & 0xFF;
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union {
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uint8_t byte_value;
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uint16_t half_value;
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uint32_t word_value;
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};
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if (devices[device][func] == NULL)
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panic("Attempting to write to config space on non-existant device\n");
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else {
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switch (req->size) {
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case sizeof(uint8_t):
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byte_value = *(uint8_t*)data;
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break;
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case sizeof(uint16_t):
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half_value = *(uint16_t*)data;
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break;
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case sizeof(uint32_t):
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word_value = *(uint32_t*)data;
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break;
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default:
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panic("invalid access size(?) for PCI configspace!\n");
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}
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}
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DPRINTF(PCIConfigAll, "write - va=%#x size=%d data=%#x\n",
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req->vaddr, req->size, word_value);
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devices[device][func]->WriteConfig(reg, req->size, word_value);
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return No_Fault;
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}
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void
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PCIConfigAll::serialize(std::ostream &os)
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{
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// code should be written
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}
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void
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PCIConfigAll::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//code should be written
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll)
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SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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END_DECLARE_SIM_OBJECT_PARAMS(PCIConfigAll)
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BEGIN_INIT_SIM_OBJECT_PARAMS(PCIConfigAll)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask")
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END_INIT_SIM_OBJECT_PARAMS(PCIConfigAll)
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CREATE_SIM_OBJECT(PCIConfigAll)
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{
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return new PCIConfigAll(getInstanceName(), tsunami, addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("PCIConfigAll", PCIConfigAll)
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