f26a289295
This patch fixes a long-standing isue with the port flow control. Before this patch the retry mechanism was shared between all different packet classes. As a result, a snoop response could get stuck behind a request waiting for a retry, even if the send/recv functions were split. This caused message-dependent deadlocks in stress-test scenarios. The patch splits the retry into one per packet (message) class. Thus, sendTimingReq has a corresponding recvReqRetry, sendTimingResp has recvRespRetry etc. Most of the changes to the code involve simply clarifying what type of request a specific object was accepting. The biggest change in functionality is in the cache downstream packet queue, facing the memory. This queue was shared by requests and snoop responses, and it is now split into two queues, each with their own flow control, but the same physical MasterPort. These changes fixes the previously seen deadlocks.
220 lines
8 KiB
C++
220 lines
8 KiB
C++
/*
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* Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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#include <iostream>
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#include <string>
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#include "base/callback.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/common/Consumer.hh"
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#include "mem/ruby/common/DataBlock.hh"
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/ruby/common/MachineID.hh"
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#include "mem/ruby/network/MessageBuffer.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/system/CacheRecorder.hh"
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#include "mem/packet.hh"
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#include "mem/qport.hh"
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#include "params/RubyController.hh"
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#include "mem/mem_object.hh"
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class Network;
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class AbstractController : public MemObject, public Consumer
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{
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public:
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typedef RubyControllerParams Params;
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AbstractController(const Params *p);
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void init();
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const Params *params() const { return (const Params *)_params; }
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const NodeID getVersion() const { return m_machineID.getNum(); }
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const MachineType getType() const { return m_machineID.getType(); }
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void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; }
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// return instance name
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void blockOnQueue(Address, MessageBuffer*);
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void unblock(Address);
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virtual MessageBuffer* getMandatoryQueue() const = 0;
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virtual AccessPermission getAccessPermission(const Address& addr) = 0;
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virtual void print(std::ostream & out) const = 0;
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virtual void wakeup() = 0;
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virtual void resetStats() = 0;
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virtual void regStats();
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virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
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virtual Sequencer* getSequencer() const = 0;
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//! These functions are used by ruby system to read/write the data blocks
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//! that exist with in the controller.
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virtual void functionalRead(const Address &addr, PacketPtr) = 0;
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void functionalMemoryRead(PacketPtr);
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//! The return value indicates the number of messages written with the
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//! data from the packet.
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virtual int functionalWriteBuffers(PacketPtr&) = 0;
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virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
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int functionalMemoryWrite(PacketPtr);
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//! Function for enqueuing a prefetch request
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virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
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{ fatal("Prefetches not implemented!");}
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//! Function for collating statistics from all the controllers of this
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//! particular type. This function should only be called from the
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//! version 0 of this controller type.
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virtual void collateStats()
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{fatal("collateStats() should be overridden!");}
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//! Set the message buffer with given name.
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virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0;
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/** A function used to return the port associated with this bus object. */
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BaseMasterPort& getMasterPort(const std::string& if_name,
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PortID idx = InvalidPortID);
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void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
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void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
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const DataBlock &block);
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void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
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const DataBlock &block, int size);
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void recvTimingResp(PacketPtr pkt);
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public:
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MachineID getMachineID() const { return m_machineID; }
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Stats::Histogram& getDelayHist() { return m_delayHistogram; }
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Stats::Histogram& getDelayVCHist(uint32_t index)
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{ return *(m_delayVCHistogram[index]); }
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protected:
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//! Profiles original cache requests including PUTs
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void profileRequest(const std::string &request);
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//! Profiles the delay associated with messages.
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void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
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void stallBuffer(MessageBuffer* buf, Address addr);
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void wakeUpBuffers(Address addr);
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void wakeUpAllBuffers(Address addr);
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void wakeUpAllBuffers();
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protected:
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NodeID m_version;
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MachineID m_machineID;
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NodeID m_clusterID;
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// MasterID used by some components of gem5.
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MasterID m_masterId;
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Network* m_net_ptr;
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bool m_is_blocking;
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std::map<Address, MessageBuffer*> m_block_map;
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typedef std::vector<MessageBuffer*> MsgVecType;
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typedef std::map< Address, MsgVecType* > WaitingBufType;
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WaitingBufType m_waiting_buffers;
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unsigned int m_in_ports;
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unsigned int m_cur_in_port;
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int m_number_of_TBEs;
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int m_transitions_per_cycle;
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unsigned int m_buffer_size;
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Cycles m_recycle_latency;
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//! Counter for the number of cycles when the transitions carried out
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//! were equal to the maximum allowed
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Stats::Scalar m_fully_busy_cycles;
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//! Histogram for profiling delay for the messages this controller
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//! cares for
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Stats::Histogram m_delayHistogram;
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std::vector<Stats::Histogram *> m_delayVCHistogram;
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//! Callback class used for collating statistics from all the
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//! controller of this type.
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class StatsCallback : public Callback
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{
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private:
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AbstractController *ctr;
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public:
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virtual ~StatsCallback() {}
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StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
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void process() {ctr->collateStats();}
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};
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/**
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* Port that forwards requests and receives responses from the
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* memory controller. It has a queue of packets not yet sent.
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*/
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class MemoryPort : public QueuedMasterPort
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{
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private:
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// Packet queues used to store outgoing requests and snoop responses.
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ReqPacketQueue reqQueue;
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SnoopRespPacketQueue snoopRespQueue;
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// Controller that operates this port.
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AbstractController *controller;
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public:
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MemoryPort(const std::string &_name, AbstractController *_controller,
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const std::string &_label);
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// Function for receiving a timing response from the peer port.
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// Currently the pkt is handed to the coherence controller
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// associated with this port.
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bool recvTimingResp(PacketPtr pkt);
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};
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/* Master port to the memory controller. */
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MemoryPort memoryPort;
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// Message Buffer for storing the response received from the
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// memory controller.
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MessageBuffer *m_responseFromMemory_ptr;
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// State that is stored in packets sent to the memory controller.
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struct SenderState : public Packet::SenderState
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{
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// Id of the machine from which the request originated.
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MachineID id;
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SenderState(MachineID _id) : id(_id)
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{}
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};
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};
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#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
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