13f8dc981f
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
110 lines
3.5 KiB
C++
110 lines
3.5 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* BadDevice implemenation
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "dev/baddev.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
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HierParams *hier, Bus *bus, const string &devicename)
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: PioDevice(name), addr(a), devname(devicename)
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{
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mmu->add_child(this, Range<Addr>(addr, addr + size));
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&BadDevice::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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}
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}
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Fault
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BadDevice::read(MemReqPtr &req, uint8_t *data)
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{
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panic("Device %s not imlpmented\n", devname);
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return No_Fault;
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}
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Fault
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BadDevice::write(MemReqPtr &req, const uint8_t *data)
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{
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panic("Device %s not imlpmented\n", devname);
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return No_Fault;
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}
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Tick
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BadDevice::cacheAccess(MemReqPtr &req)
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{
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return curTick;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<HierParams *> hier;
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SimObjectParam<Bus*> io_bus;
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Param<string> devicename;
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END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
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BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM(devicename, "Name of device to error on")
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END_INIT_SIM_OBJECT_PARAMS(BadDevice)
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CREATE_SIM_OBJECT(BadDevice)
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{
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return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus,
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devicename);
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}
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REGISTER_SIM_OBJECT("BadDevice", BadDevice)
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