877435950c
Add a set of scripts to automatically test checkpointing in the regression framework. The checkpointing tests are similar to the switcheroo tests, but instead of switching between CPUs, they checkpoint the system and restore from the checkpoint again. This is done at regular intervals, typically while booting Linux. The implementation is fairly straight forward, with the exception that we have to work around gem5's inability to restore from a checkpoint after a system has been instantiated. We work around this by forking off child processes that does the actual simulation and never instantiate a system in the parent process unless a maximum checkpoint count is reached (in which case we just simulate the system to completion in the parent). Checkpoint testing is currently only enabled 32- and 64-bit ARM systems using atomic CPUs. Note: An unfortunate side-effect of forking is that every new process will overwrite the stats and terminal output from the previous process. This means that the output directory only contains data from the last checkpoint.
740 lines
87 KiB
Text
740 lines
87 KiB
Text
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---------- Begin Simulation Statistics ----------
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final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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host_inst_rate 976886 # Simulator instruction rate (inst/s)
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host_mem_usage 567972 # Number of bytes of host memory used
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host_op_rate 1189202 # Simulator op (including micro ops) rate (op/s)
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host_seconds 146.15 # Real time elapsed on the host
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host_tick_rate 19047880334 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 142772879 # Number of instructions simulated
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sim_ops 173803124 # Number of ops (including micro ops) simulated
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sim_seconds 2.783867 # Number of seconds simulated
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sim_ticks 2783867052000 # Number of ticks simulated
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system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
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system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
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system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
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system.cf0.dma_write_txs 631 # Number of DMA write transactions.
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system.clk_domain.clock 1000 # Clock period in ticks
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system.cpu.Branches 36396981 # Number of branches fetched
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system.cpu.committedInsts 142772879 # Number of instructions committed
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system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed
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system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses)
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system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits
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system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses
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system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses
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system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses
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system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses
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system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses)
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system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses)
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system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits
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system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses
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system.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses
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system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses
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system.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses
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system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses)
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system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits
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system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
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system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
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system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses
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system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
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system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
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system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses
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system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits
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system.cpu.dcache.overall_hits::total 52864242 # number of overall hits
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system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
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system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses
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system.cpu.dcache.overall_misses::total 814074 # number of overall misses
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system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
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system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
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system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks.
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system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses
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system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
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system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.dcache.tags.replacements 819402 # number of replacements
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system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks.
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system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses
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system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
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system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks.
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system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks
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system.cpu.dcache.writebacks::total 682059 # number of writebacks
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system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
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system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
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system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
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system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
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system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
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system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
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system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
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system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
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system.cpu.dtb.accesses 54660704 # DTB accesses
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
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system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.hits 54650675 # DTB hits
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.misses 10029 # DTB misses
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system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
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system.cpu.dtb.read_accesses 31534804 # DTB read accesses
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system.cpu.dtb.read_hits 31526223 # DTB read hits
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system.cpu.dtb.read_misses 8581 # DTB read misses
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system.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated
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system.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated
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system.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst
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system.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency
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system.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency
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system.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency
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system.cpu.dtb.walker.walks 10029 # Table walker walks requested
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system.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution
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system.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution
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system.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution
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system.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors
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system.cpu.dtb.write_accesses 23125900 # DTB write accesses
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system.cpu.dtb.write_hits 23124452 # DTB write hits
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system.cpu.dtb.write_misses 1448 # DTB write misses
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system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses
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system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses
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system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses
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system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses
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system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits
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system.cpu.icache.overall_hits::total 145342721 # number of overall hits
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system.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses
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system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses
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system.cpu.icache.overall_misses::total 1699732 # number of overall misses
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system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
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system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
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system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks.
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system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses
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system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor
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system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
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system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu.icache.tags.replacements 1699214 # number of replacements
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system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks.
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system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses
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system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use
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system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks.
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system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
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system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
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system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
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system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.accesses 147044108 # DTB accesses
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.hits 147039346 # DTB hits
|
|
system.cpu.itb.inst_accesses 147044108 # ITB inst accesses
|
|
system.cpu.itb.inst_hits 147039346 # ITB inst hits
|
|
system.cpu.itb.inst_misses 4762 # ITB inst misses
|
|
system.cpu.itb.misses 4762 # DTB misses
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency
|
|
system.cpu.itb.walker.walks 4762 # Table walker walks requested
|
|
system.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution
|
|
system.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 181764 # number of overall misses
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.replacements 110026 # number of replacements
|
|
system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses
|
|
system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 101897 # number of writebacks
|
|
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
|
|
system.cpu.numCycles 5567737188 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles
|
|
system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written
|
|
system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls
|
|
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
|
|
system.cpu.num_fp_insts 11484 # number of float instructions
|
|
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
|
|
system.cpu.num_func_calls 16873899 # number of times a function call or return occured
|
|
system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles
|
|
system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses
|
|
system.cpu.num_int_insts 153162683 # number of integer instructions
|
|
system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written
|
|
system.cpu.num_load_insts 31855884 # Number of load instructions
|
|
system.cpu.num_mem_refs 55939276 # number of memory refs
|
|
system.cpu.num_store_insts 24083392 # Number of store instructions
|
|
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
|
|
system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction
|
|
system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
|
|
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
|
|
system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction
|
|
system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu.op_class::total 177219912 # Class of executed instruction
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 22778 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 240 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 240 # number of demand (read+write) misses
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.overall_misses::realview.ide 240 # number of overall misses
|
|
system.iocache.overall_misses::total 240 # number of overall misses
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.data_accesses 328176 # Number of data accesses
|
|
system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.replacements 36430 # number of replacements
|
|
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
|
|
system.iocache.tags.tag_accesses 328176 # Number of tag accesses
|
|
system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.writebacks::writebacks 36190 # number of writebacks
|
|
system.iocache.writebacks::total 36190 # number of writebacks
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoop_fanout::samples 359045 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 359045 # Request fanout histogram
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.trans_dist::ReadReq 74227 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 74227 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27546 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27546 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 138087 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
|
|
system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
|
|
---------- End Simulation Statistics ----------
|