00536b0efc
This patch aligns how the response routing is done in the RubyPort, using the SenderState for both memory and I/O accesses. Before this patch, only the I/O used the SenderState, whereas the memory accesses relied on the src field in the packet. With this patch we shift to using SenderState in both cases, thus not relying on the src field any longer.
567 lines
19 KiB
C++
567 lines
19 KiB
C++
/*
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* Copyright (c) 2012-2013 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* Copyright (c) 2011 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "debug/Config.hh"
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#include "debug/Drain.hh"
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#include "debug/Ruby.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/RubyPort.hh"
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#include "mem/simple_mem.hh"
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#include "sim/full_system.hh"
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#include "sim/system.hh"
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RubyPort::RubyPort(const Params *p)
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: MemObject(p), m_version(p->version), m_controller(NULL),
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m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
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system(p->system),
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pioMasterPort(csprintf("%s.pio-master-port", name()), this),
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pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
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memMasterPort(csprintf("%s.mem-master-port", name()), this),
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memSlavePort(csprintf("%s-mem-slave-port", name()), this,
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p->ruby_system, p->access_backing_store, -1),
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gotAddrRanges(p->port_master_connection_count), drainManager(NULL)
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{
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assert(m_version != -1);
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// create the slave ports based on the number of connected ports
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for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
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slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
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i), this, p->ruby_system, p->access_backing_store, i));
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}
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// create the master ports based on the number of connected ports
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for (size_t i = 0; i < p->port_master_connection_count; ++i) {
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master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
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name(), i), this));
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}
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}
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void
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RubyPort::init()
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{
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assert(m_controller != NULL);
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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m_mandatory_q_ptr->setSender(this);
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}
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BaseMasterPort &
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RubyPort::getMasterPort(const std::string &if_name, PortID idx)
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{
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if (if_name == "mem_master_port") {
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return memMasterPort;
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}
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if (if_name == "pio_master_port") {
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return pioMasterPort;
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}
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// used by the x86 CPUs to connect the interrupt PIO and interrupt slave
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// port
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if (if_name != "master") {
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// pass it along to our super class
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return MemObject::getMasterPort(if_name, idx);
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} else {
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if (idx >= static_cast<PortID>(master_ports.size())) {
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panic("RubyPort::getMasterPort: unknown index %d\n", idx);
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}
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return *master_ports[idx];
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}
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}
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BaseSlavePort &
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RubyPort::getSlavePort(const std::string &if_name, PortID idx)
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{
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if (if_name == "mem_slave_port") {
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return memSlavePort;
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}
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if (if_name == "pio_slave_port")
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return pioSlavePort;
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// used by the CPUs to connect the caches to the interconnect, and
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// for the x86 case also the interrupt master
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if (if_name != "slave") {
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// pass it along to our super class
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return MemObject::getSlavePort(if_name, idx);
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} else {
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if (idx >= static_cast<PortID>(slave_ports.size())) {
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panic("RubyPort::getSlavePort: unknown index %d\n", idx);
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}
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return *slave_ports[idx];
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}
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}
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RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
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RubyPort *_port)
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: QueuedMasterPort(_name, _port, queue), queue(*_port, *this)
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{
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DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
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}
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RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
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RubyPort *_port)
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: QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
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{
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DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
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}
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RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
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RubyPort *_port)
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: QueuedMasterPort(_name, _port, queue), queue(*_port, *this)
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{
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DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
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}
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RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
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RubySystem *_system,
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bool _access_backing_store, PortID id)
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: QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
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ruby_system(_system), access_backing_store(_access_backing_store)
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{
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DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
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}
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bool
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RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
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{
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RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
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DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
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// send next cycle
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ruby_port->pioSlavePort.schedTimingResp(
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pkt, curTick() + g_system_ptr->clockPeriod());
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return true;
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}
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bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
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{
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// got a response from a device
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assert(pkt->isResponse());
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// First we must retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
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MemSlavePort *port = senderState->port;
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assert(port != NULL);
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delete senderState;
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// In FS mode, ruby memory will receive pio responses from devices
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// and it must forward these responses back to the particular CPU.
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DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
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pkt->getAddr(), port->name());
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// attempt to send the response in the next cycle
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port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
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return true;
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}
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bool
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RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
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{
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RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
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for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
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AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
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for (auto it = l.begin(); it != l.end(); ++it) {
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if (it->contains(pkt->getAddr())) {
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// generally it is not safe to assume success here as
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// the port could be blocked
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bool M5_VAR_USED success =
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ruby_port->master_ports[i]->sendTimingReq(pkt);
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assert(success);
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return true;
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}
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}
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}
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panic("Should never reach here!\n");
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}
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bool
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RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
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{
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DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
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pkt->getAddr(), id);
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RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
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if (pkt->memInhibitAsserted())
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panic("RubyPort should never see an inhibited request\n");
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// Check for pio requests and directly send them to the dedicated
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// pio port.
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if (!isPhysMemAddress(pkt->getAddr())) {
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assert(ruby_port->memMasterPort.isConnected());
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DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n",
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pkt->getAddr());
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// Save the port in the sender state object to be used later to
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// route the response
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pkt->pushSenderState(new SenderState(this));
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// send next cycle
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ruby_port->memMasterPort.schedTimingReq(pkt,
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curTick() + g_system_ptr->clockPeriod());
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return true;
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}
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assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
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RubySystem::getBlockSizeBytes());
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// Submit the ruby request
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RequestStatus requestStatus = ruby_port->makeRequest(pkt);
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// If the request successfully issued then we should return true.
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// Otherwise, we need to tell the port to retry at a later point
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// and return false.
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if (requestStatus == RequestStatus_Issued) {
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// Save the port in the sender state object to be used later to
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// route the response
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pkt->pushSenderState(new SenderState(this));
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DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
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pkt->getAddr());
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return true;
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}
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//
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// Unless one is using the ruby tester, record the stalled M5 port for
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// later retry when the sequencer becomes free.
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//
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if (!ruby_port->m_usingRubyTester) {
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ruby_port->addToRetryList(this);
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}
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DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n",
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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return false;
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}
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void
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RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
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{
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DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
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// Check for pio requests and directly send them to the dedicated
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// pio port.
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if (!isPhysMemAddress(pkt->getAddr())) {
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RubyPort *ruby_port M5_VAR_USED = static_cast<RubyPort *>(&owner);
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assert(ruby_port->memMasterPort.isConnected());
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DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
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panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n");
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}
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assert(pkt->getAddr() + pkt->getSize() <=
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line_address(Address(pkt->getAddr())).getAddress() +
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RubySystem::getBlockSizeBytes());
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bool accessSucceeded = false;
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bool needsResponse = pkt->needsResponse();
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// Do the functional access on ruby memory
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if (pkt->isRead()) {
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accessSucceeded = ruby_system->functionalRead(pkt);
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} else if (pkt->isWrite()) {
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accessSucceeded = ruby_system->functionalWrite(pkt);
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} else {
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panic("Unsupported functional command %s\n", pkt->cmdString());
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}
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// Unless the requester explicitly said otherwise, generate an error if
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// the functional request failed
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if (!accessSucceeded && !pkt->suppressFuncError()) {
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fatal("Ruby functional %s failed for address %#x\n",
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pkt->isWrite() ? "write" : "read", pkt->getAddr());
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}
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if (access_backing_store) {
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// The attached physmem contains the official version of data.
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// The following command performs the real functional access.
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// This line should be removed once Ruby supplies the official version
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// of data.
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ruby_system->getPhysMem()->functionalAccess(pkt);
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}
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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pkt->setFunctionalResponseStatus(accessSucceeded);
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}
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DPRINTF(RubyPort, "Functional access %s!\n",
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accessSucceeded ? "successful":"failed");
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}
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void
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RubyPort::ruby_hit_callback(PacketPtr pkt)
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{
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DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
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pkt->getAddr());
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// The packet was destined for memory and has not yet been turned
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// into a response
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assert(system->isMemAddr(pkt->getAddr()));
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assert(pkt->isRequest());
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// First we must retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
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MemSlavePort *port = senderState->port;
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assert(port != NULL);
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delete senderState;
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port->hitCallback(pkt);
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//
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// If we had to stall the MemSlavePorts, wake them up because the sequencer
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// likely has free resources now.
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//
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if (!retryList.empty()) {
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//
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// Record the current list of ports to retry on a temporary list before
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// calling sendRetry on those ports. sendRetry will cause an
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// immediate retry, which may result in the ports being put back on the
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// list. Therefore we want to clear the retryList before calling
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// sendRetry.
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//
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std::vector<MemSlavePort *> curRetryList(retryList);
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retryList.clear();
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for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
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DPRINTF(RubyPort,
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"Sequencer may now be free. SendRetry to port %s\n",
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(*i)->name());
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(*i)->sendRetry();
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}
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}
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testDrainComplete();
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}
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void
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RubyPort::testDrainComplete()
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{
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//If we weren't able to drain before, we might be able to now.
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if (drainManager != NULL) {
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unsigned int drainCount = outstandingCount();
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DPRINTF(Drain, "Drain count: %u\n", drainCount);
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if (drainCount == 0) {
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DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
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drainManager->signalDrainDone();
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// Clear the drain manager once we're done with it.
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drainManager = NULL;
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}
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}
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}
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unsigned int
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RubyPort::getChildDrainCount(DrainManager *dm)
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{
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int count = 0;
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if (memMasterPort.isConnected()) {
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count += memMasterPort.drain(dm);
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DPRINTF(Config, "count after pio check %d\n", count);
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}
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for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
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count += (*p)->drain(dm);
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DPRINTF(Config, "count after slave port check %d\n", count);
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}
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for (std::vector<PioMasterPort *>::iterator p = master_ports.begin();
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p != master_ports.end(); ++p) {
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count += (*p)->drain(dm);
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DPRINTF(Config, "count after master port check %d\n", count);
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}
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DPRINTF(Config, "final count %d\n", count);
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return count;
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}
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unsigned int
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RubyPort::drain(DrainManager *dm)
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{
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if (isDeadlockEventScheduled()) {
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descheduleDeadlockEvent();
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}
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//
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// If the RubyPort is not empty, then it needs to clear all outstanding
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// requests before it should call drainManager->signalDrainDone()
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//
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DPRINTF(Config, "outstanding count %d\n", outstandingCount());
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bool need_drain = outstandingCount() > 0;
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//
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// Also, get the number of child ports that will also need to clear
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// their buffered requests before they call drainManager->signalDrainDone()
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//
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unsigned int child_drain_count = getChildDrainCount(dm);
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// Set status
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if (need_drain) {
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drainManager = dm;
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DPRINTF(Drain, "RubyPort not drained\n");
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setDrainState(Drainable::Draining);
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return child_drain_count + 1;
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}
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drainManager = NULL;
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setDrainState(Drainable::Drained);
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return child_drain_count;
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}
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void
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RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
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{
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bool needsResponse = pkt->needsResponse();
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// Unless specified at configuraiton, all responses except failed SC
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// and Flush operations access M5 physical memory.
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bool accessPhysMem = access_backing_store;
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if (pkt->isLLSC()) {
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if (pkt->isWrite()) {
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if (pkt->req->getExtraData() != 0) {
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//
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// Successful SC packets convert to normal writes
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//
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pkt->convertScToWrite();
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} else {
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//
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// Failed SC packets don't access physical memory and thus
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// the RubyPort itself must convert it to a response.
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//
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accessPhysMem = false;
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}
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} else {
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//
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// All LL packets convert to normal loads so that M5 PhysMem does
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// not lock the blocks.
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//
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pkt->convertLlToRead();
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}
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}
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// Flush requests don't access physical memory
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if (pkt->isFlush()) {
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accessPhysMem = false;
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}
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DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
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|
|
if (accessPhysMem) {
|
|
ruby_system->getPhysMem()->functionalAccess(pkt);
|
|
} else if (needsResponse) {
|
|
pkt->makeResponse();
|
|
}
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
if (needsResponse) {
|
|
DPRINTF(RubyPort, "Sending packet back over port\n");
|
|
// send next cycle
|
|
schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
|
|
} else {
|
|
delete pkt;
|
|
}
|
|
|
|
DPRINTF(RubyPort, "Hit callback done!\n");
|
|
}
|
|
|
|
AddrRangeList
|
|
RubyPort::PioSlavePort::getAddrRanges() const
|
|
{
|
|
// at the moment the assumption is that the master does not care
|
|
AddrRangeList ranges;
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
|
|
|
for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
|
|
ranges.splice(ranges.begin(),
|
|
ruby_port->master_ports[i]->getAddrRanges());
|
|
}
|
|
for (const auto M5_VAR_USED &r : ranges)
|
|
DPRINTF(RubyPort, "%s\n", r.to_string());
|
|
return ranges;
|
|
}
|
|
|
|
bool
|
|
RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
|
|
{
|
|
RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
|
|
return ruby_port->system->isMemAddr(addr);
|
|
}
|
|
|
|
void
|
|
RubyPort::ruby_eviction_callback(const Address& address)
|
|
{
|
|
DPRINTF(RubyPort, "Sending invalidations.\n");
|
|
// This request is deleted in the stack-allocated packet destructor
|
|
// when this function exits
|
|
// TODO: should this really be using funcMasterId?
|
|
RequestPtr req =
|
|
new Request(address.getAddress(), 0, 0, Request::funcMasterId);
|
|
// Use a single packet to signal all snooping ports of the invalidation.
|
|
// This assumes that snooping ports do NOT modify the packet/request
|
|
Packet pkt(req, MemCmd::InvalidationReq);
|
|
for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
|
|
// check if the connected master port is snooping
|
|
if ((*p)->isSnooping()) {
|
|
// send as a snoop request
|
|
(*p)->sendTimingSnoopReq(&pkt);
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
RubyPort::PioMasterPort::recvRangeChange()
|
|
{
|
|
RubyPort &r = static_cast<RubyPort &>(owner);
|
|
r.gotAddrRanges--;
|
|
if (r.gotAddrRanges == 0 && FullSystem) {
|
|
r.pioSlavePort.sendRangeChange();
|
|
}
|
|
}
|