f16c0a4a90
Draining is currently done by traversing the SimObject graph and calling drain()/drainResume() on the SimObjects. This is not ideal when non-SimObjects (e.g., ports) need draining since this means that SimObjects owning those objects need to be aware of this. This changeset moves the responsibility for finding objects that need draining from SimObjects and the Python-side of the simulator to the DrainManager. The DrainManager now maintains a set of all objects that need draining. To reduce the overhead in classes owning non-SimObjects that need draining, objects inheriting from Drainable now automatically register with the DrainManager. If such an object is destroyed, it is automatically unregistered. This means that drain() and drainResume() should never be called directly on a Drainable object. While implementing the new functionality, the DrainManager has now been made thread safe. In practice, this means that it takes a lock whenever it manipulates the set of Drainable objects since SimObjects in different threads may create Drainable objects dynamically. Similarly, the drain counter is now an atomic_uint, which ensures that it is manipulated correctly when objects signal that they are done draining. A nice side effect of these changes is that it makes the drain state changes stricter, which the simulation scripts can exploit to avoid redundant drains.
131 lines
4.5 KiB
C++
Executable file
131 lines
4.5 KiB
C++
Executable file
/*
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* Copyright (c) 2012-2013, 2015 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Thomas Grocutt
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*/
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#ifndef __ARCH_ARM_STAGE2_MMU_HH__
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#define __ARCH_ARM_STAGE2_MMU_HH__
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#include "arch/arm/faults.hh"
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#include "arch/arm/tlb.hh"
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#include "dev/dma_device.hh"
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#include "mem/request.hh"
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#include "params/ArmStage2MMU.hh"
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#include "sim/eventq.hh"
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namespace ArmISA {
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class Stage2MMU : public SimObject
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{
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private:
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TLB *_stage1Tlb;
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/** The TLB that will cache the stage 2 look ups. */
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TLB *_stage2Tlb;
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protected:
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/** Port to issue translation requests from */
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DmaPort port;
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/** Request id for requests generated by this MMU */
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MasterID masterId;
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public:
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/** This translation class is used to trigger the data fetch once a timing
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translation returns the translated physical address */
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class Stage2Translation : public BaseTLB::Translation
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{
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private:
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uint8_t *data;
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int numBytes;
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Request req;
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Event *event;
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Stage2MMU &parent;
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Addr oVAddr;
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public:
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Fault fault;
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Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
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Addr _oVAddr);
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void
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markDelayed() {}
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void
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finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode);
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void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
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{
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numBytes = size;
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req.setVirt(0, vaddr, size, flags, masterId, 0);
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}
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Fault translateTiming(ThreadContext *tc)
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{
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return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
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}
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};
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typedef ArmStage2MMUParams Params;
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Stage2MMU(const Params *p);
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/**
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* Get the port that ultimately belongs to the stage-two MMU, but
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* is used by the two table walkers, and is exposed externally and
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* connected through the stage-one table walker.
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*/
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DmaPort& getPort() { return port; }
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Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
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uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
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Fault readDataTimed(ThreadContext *tc, Addr descAddr,
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Stage2Translation *translation, int numBytes,
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Request::Flags flags);
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TLB* stage1Tlb() const { return _stage1Tlb; }
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TLB* stage2Tlb() const { return _stage2Tlb; }
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};
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} // namespace ArmISA
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#endif //__ARCH_ARM_STAGE2_MMU_HH__
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