f15e492375
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext). Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out. Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers. SConscript: Include new file, cpu_exec_context.cc. arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_memory.cc: arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: arch/alpha/isa/decoder.isa: arch/alpha/stacktrace.cc: arch/alpha/vtophys.cc: base/remote_gdb.cc: cpu/intr_control.cc: Avoid directly accessing objects within the XC. arch/alpha/ev5.cc: Avoid directly accessing objects within the XC. KernelStats have been moved to the BaseCPU instead of the XC. arch/alpha/isa_traits.hh: Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext. cpu/base.cc: Place kernel stats within the BaseCPU instead of the ExecContext. For now comment out the profiling code sampling until its exact location is decided upon. cpu/base.hh: Kernel stats are now in the BaseCPU instead of the ExecContext. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. cpu/exetrace.cc: Remove unneeded include of exec_context.hh. cpu/intr_control.hh: cpu/o3/alpha_cpu_builder.cc: Remove unneeded include of exec_context.hh cpu/o3/alpha_cpu.hh: cpu/o3/alpha_cpu_impl.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: cpu/simple/cpu.cc: cpu/simple/cpu.hh: Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details. Also avoid accessing anything directly from the XC. cpu/pc_event.cc: Avoid accessing objects directly from the XC. dev/tsunami_cchip.cc: Avoid accessing objects directly within the XC> kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/linux/linux_threadinfo.hh: kern/tru64/dump_mbuf.cc: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: sim/syscall_emul.cc: sim/syscall_emul.hh: Avoid accessing objects directly within the XC. kern/kernel_stats.cc: kern/kernel_stats.hh: Kernel stats no longer exist within the XC. kern/system_events.cc: Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU. sim/process.cc: sim/process.hh: Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over. cpu/cpu_exec_context.cc: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. cpu/cpu_exec_context.hh: Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU. Remove kernel stats from the ExecContext. sim/pseudo_inst.cc: Kernel stats now live within the CPU. Avoid accessing objects directly within the XC. --HG-- rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
366 lines
11 KiB
C++
366 lines
11 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/cprintf.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "mem/cache/cache.hh" // for dynamic cast
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#include "mem/mem_interface.hh"
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#include "sim/builder.hh"
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#include "sim/sim_events.hh"
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#include "sim/stats.hh"
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#include "cpu/o3/alpha_cpu.hh"
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#include "cpu/o3/alpha_params.hh"
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#include "cpu/o3/comm.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/osfpal.hh"
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#include "arch/alpha/isa_traits.hh"
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#endif
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template <class Impl>
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AlphaFullCPU<Impl>::AlphaFullCPU(Params ¶ms)
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: FullO3CPU<Impl>(params)
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n");
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this->fetch.setCPU(this);
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this->decode.setCPU(this);
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this->rename.setCPU(this);
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this->iew.setCPU(this);
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this->commit.setCPU(this);
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this->rob.setCPU(this);
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::regStats()
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{
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// Register stats for everything that has stats.
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this->fullCPURegStats();
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this->fetch.regStats();
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this->decode.regStats();
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this->rename.regStats();
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this->iew.regStats();
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this->commit.regStats();
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}
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#if !FULL_SYSTEM
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// Will probably need to know which thread is calling syscall
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// Will need to pass that information in to the DynInst when it is constructed,
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// so that this call can be made with the proper thread number.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::syscall(short thread_num)
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{
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DPRINTF(FullCPU, "AlphaFullCPU: Syscall() called.\n\n");
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// Commit stage needs to run as well.
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this->commit.tick();
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squashStages();
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// Temporarily increase this by one to account for the syscall
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// instruction.
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++(this->funcExeInst);
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// Copy over all important state to xc once all the unrolling is done.
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copyToXC();
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// This is hardcoded to thread 0 while the CPU is only single threaded.
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this->thread[0]->syscall();
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// Copy over all important state back to CPU.
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copyFromXC();
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// Decrease funcExeInst by one as the normal commit will handle
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// incrememnting it.
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--(this->funcExeInst);
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}
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// This is not a pretty function, and should only be used if it is necessary
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// to fake having everything squash all at once (ie for non-full system
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// syscalls). Maybe put this at the FullCPU level?
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template <class Impl>
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void
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AlphaFullCPU<Impl>::squashStages()
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{
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InstSeqNum rob_head = this->rob.readHeadSeqNum();
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// Now hack the time buffer to put this sequence number in the places
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// where the stages might read it.
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for (int i = 0; i < 5; ++i)
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{
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this->timeBuffer.access(-i)->commitInfo.doneSeqNum = rob_head;
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}
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this->fetch.squash(this->rob.readHeadNextPC());
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this->fetchQueue.advance();
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this->decode.squash();
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this->decodeQueue.advance();
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this->rename.squash();
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this->renameQueue.advance();
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this->renameQueue.advance();
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// Be sure to advance the IEW queues so that the commit stage doesn't
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// try to set an instruction as completed at the same time that it
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// might be deleting it.
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this->iew.squash();
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this->iewQueue.advance();
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this->iewQueue.advance();
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// Needs to tell the LSQ to write back all of its data
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this->iew.lsqWriteback();
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this->rob.squash(rob_head);
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this->commit.setSquashing();
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// Now hack the time buffer to clear the sequence numbers in the places
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// where the stages might read it.?
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for (int i = 0; i < 5; ++i)
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{
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this->timeBuffer.access(-i)->commitInfo.doneSeqNum = 0;
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}
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}
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#endif // FULL_SYSTEM
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyToXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i);
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this->cpuXC->setIntReg(i, this->regFile.readIntReg(renamed_reg));
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DPRINTF(FullCPU, "FullCPU: Copying register %i, has data %lli.\n",
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renamed_reg, this->regFile.intRegFile[renamed_reg]);
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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this->cpuXC->setFloatRegDouble(i,
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this->regFile.readFloatRegDouble(renamed_reg));
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this->cpuXC->setFloatRegInt(i,
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this->regFile.readFloatRegInt(renamed_reg));
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}
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/*
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this->cpuXC->regs.miscRegs.fpcr = this->regFile.miscRegs.fpcr;
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this->cpuXC->regs.miscRegs.uniq = this->regFile.miscRegs.uniq;
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this->cpuXC->regs.miscRegs.lock_flag = this->regFile.miscRegs.lock_flag;
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this->cpuXC->regs.miscRegs.lock_addr = this->regFile.miscRegs.lock_addr;
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*/
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this->cpuXC->setPC(this->rob.readHeadPC());
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this->cpuXC->setNextPC(this->cpuXC->readPC()+4);
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#if !FULL_SYSTEM
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this->cpuXC->setFuncExeInst(this->funcExeInst);
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#endif
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}
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// This function will probably mess things up unless the ROB is empty and
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// there are no instructions in the pipeline.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::copyFromXC()
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{
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PhysRegIndex renamed_reg;
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// First loop through the integer registers.
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for (int i = 0; i < AlphaISA::NumIntRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i);
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DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, "
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"now has data %lli.\n",
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renamed_reg, this->regFile.intRegFile[renamed_reg],
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this->cpuXC->readIntReg(i));
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this->regFile.setIntReg(renamed_reg, this->cpuXC->readIntReg(i));
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}
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// Then loop through the floating point registers.
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for (int i = 0; i < AlphaISA::NumFloatRegs; ++i)
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{
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renamed_reg = this->renameMap.lookup(i + AlphaISA::FP_Base_DepTag);
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this->regFile.setFloatRegDouble(renamed_reg,
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this->cpuXC->readFloatRegDouble(i));
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this->regFile.setFloatRegInt(renamed_reg,
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this->cpuXC->readFloatRegInt(i));
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}
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/*
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// Then loop through the misc registers.
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this->regFile.miscRegs.fpcr = this->cpuXC->regs.miscRegs.fpcr;
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this->regFile.miscRegs.uniq = this->cpuXC->regs.miscRegs.uniq;
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this->regFile.miscRegs.lock_flag = this->cpuXC->regs.miscRegs.lock_flag;
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this->regFile.miscRegs.lock_addr = this->cpuXC->regs.miscRegs.lock_addr;
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*/
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// Then finally set the PC and the next PC.
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// regFile.pc = cpuXC->regs.pc;
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// regFile.npc = cpuXC->regs.npc;
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#if !FULL_SYSTEM
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this->funcExeInst = this->cpuXC->readFuncExeInst();
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#endif
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}
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#if FULL_SYSTEM
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template <class Impl>
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int
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AlphaFullCPU<Impl>::readIntrFlag()
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{
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return this->regFile.readIntrFlag();
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::setIntrFlag(int val)
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{
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this->regFile.setIntrFlag(val);
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}
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// Can force commit stage to squash and stuff.
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template <class Impl>
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Fault
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AlphaFullCPU<Impl>::hwrei()
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{
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if (!inPalMode())
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return UnimplementedOpcodeFault;
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this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
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// kernelStats.hwrei();
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if ((this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
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// AlphaISA::swap_palshadow(®s, false);
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this->checkInterrupts = true;
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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template <class Impl>
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bool
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AlphaFullCPU<Impl>::simPalCheck(int palFunc)
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{
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// kernelStats.callpal(palFunc);
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switch (palFunc) {
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case PAL::halt:
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halt();
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if (--System::numSystemsRunning == 0)
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new SimExitEvent("all cpus halted");
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break;
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case PAL::bpt:
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case PAL::bugchk:
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if (this->system->breakpoint())
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return false;
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break;
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}
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return true;
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}
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// Probably shouldn't be able to switch to the trap handler as quickly as
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// this. Also needs to get the exception restart address from the commit
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// stage.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::trap(Fault fault)
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{
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// Keep in mind that a trap may be initiated by fetch if there's a TLB
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// miss
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uint64_t PC = this->commit.readCommitPC();
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DPRINTF(Fault, "Fault %s\n", fault ? fault->name : "name");
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this->recordEvent(csprintf("Fault %s", fault ? fault->name : "name"));
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// kernelStats.fault(fault);
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if (fault == ArithmeticFault)
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panic("Arithmetic traps are unimplemented!");
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// exception restart address - Get the commit PC
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if (fault != InterruptFault || !inPalMode(PC))
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this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR, PC);
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if (fault == PalFault || fault == ArithmeticFault /* ||
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fault == InterruptFault && !PC_PAL(regs.pc) */) {
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// traps... skip faulting instruction
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AlphaISA::MiscReg ipr_exc_addr =
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this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR);
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this->regFile.miscRegs.setReg(AlphaISA::IPR_EXC_ADDR,
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ipr_exc_addr + 4);
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}
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if (!inPalMode(PC))
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swapPALShadow(true);
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this->regFile.setPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_PAL_BASE) +
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AlphaISA::fault_addr(fault) );
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this->regFile.setNextPC(PC + sizeof(MachInst));
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}
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template <class Impl>
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void
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AlphaFullCPU<Impl>::processInterrupts()
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{
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// Check for interrupts here. For now can copy the code that exists
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// within isa_fullsys_traits.hh.
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}
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// swap_palshadow swaps in the values of the shadow registers and
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// swaps them with the values of the physical registers that map to the
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// same logical index.
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template <class Impl>
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void
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AlphaFullCPU<Impl>::swapPALShadow(bool use_shadow)
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{
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if (palShadowEnabled == use_shadow)
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panic("swap_palshadow: wrong PAL shadow state");
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palShadowEnabled = use_shadow;
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// Will have to lookup in rename map to get physical registers, then
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// swap.
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}
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#endif // FULL_SYSTEM
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