f15e492375
The major change is renaming the old ExecContext to CPUExecContext, and creating two new classes, ExecContext (an abstract class), and ProxyExecContext (a templated class that derives from ExecContext).
Code outside of the CPU continues to use ExecContext as normal (other than not being able to access variables within the XC). The CPU uses the CPUExecContext, or however else it stores its own state. It then creates a ProxyExecContext, templated on the class used to hold its state. This proxy is passed to any code outside of the CPU that needs to access the XC. This allows code outside of the CPU to use the ExecContext interface to access any state needed, without knowledge of how that state is laid out.
Note that these changes will not compile without the accompanying revision to automatically rename the shadow registers.
SConscript:
Include new file, cpu_exec_context.cc.
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
arch/alpha/isa/decoder.isa:
arch/alpha/stacktrace.cc:
arch/alpha/vtophys.cc:
base/remote_gdb.cc:
cpu/intr_control.cc:
Avoid directly accessing objects within the XC.
arch/alpha/ev5.cc:
Avoid directly accessing objects within the XC.
KernelStats have been moved to the BaseCPU instead of the XC.
arch/alpha/isa_traits.hh:
Remove clearIprs(). It wasn't used very often and it did not work well with the proxy ExecContext.
cpu/base.cc:
Place kernel stats within the BaseCPU instead of the ExecContext.
For now comment out the profiling code sampling until its exact location is decided upon.
cpu/base.hh:
Kernel stats are now in the BaseCPU instead of the ExecContext.
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/memtest/memtest.cc:
cpu/memtest/memtest.hh:
Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details.
cpu/exetrace.cc:
Remove unneeded include of exec_context.hh.
cpu/intr_control.hh:
cpu/o3/alpha_cpu_builder.cc:
Remove unneeded include of exec_context.hh
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Changes to support rename of old ExecContext to CPUExecContext. See changeset for more details.
Also avoid accessing anything directly from the XC.
cpu/pc_event.cc:
Avoid accessing objects directly from the XC.
dev/tsunami_cchip.cc:
Avoid accessing objects directly within the XC>
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/linux/linux_threadinfo.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
Avoid accessing objects directly within the XC.
kern/kernel_stats.cc:
kern/kernel_stats.hh:
Kernel stats no longer exist within the XC.
kern/system_events.cc:
Avoid accessing objects directly within the XC. Also kernel stats are now in the BaseCPU.
sim/process.cc:
sim/process.hh:
Avoid accessing regs directly within an ExecContext. Instead use a CPUExecContext to initialize the registers and copy them over.
cpu/cpu_exec_context.cc:
Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
cpu/cpu_exec_context.hh:
Rename old ExecContext to CPUExecContext. This is used by the old CPU models to store any necessary architectural state. Also include the ProxyExecContext, which is used to access the CPUExecContext's state in code outside of the CPU.
Remove kernel stats from the ExecContext.
sim/pseudo_inst.cc:
Kernel stats now live within the CPU.
Avoid accessing objects directly within the XC.
--HG--
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : a75393a8945c80cca225b5e9d9c22a16609efb85
671 lines
19 KiB
C++
671 lines
19 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "arch/alpha/alpha_memory.hh"
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#include "arch/alpha/isa_traits.hh"
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#include "arch/alpha/osfpal.hh"
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#include "base/kgdb.h"
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#include "base/remote_gdb.hh"
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#include "base/stats/events.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/cpu_exec_context.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/fast/cpu.hh"
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#include "kern/kernel_stats.hh"
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#include "sim/debug.hh"
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#include "sim/sim_events.hh"
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#if FULL_SYSTEM
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using namespace EV5;
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
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{
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if (regs->pal_shadow == use_shadow)
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panic("swap_palshadow: wrong PAL shadow state");
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regs->pal_shadow = use_shadow;
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for (int i = 0; i < NumIntRegs; i++) {
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if (reg_redir[i]) {
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IntReg temp = regs->intRegFile[i];
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regs->intRegFile[i] = regs->palregs[i];
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regs->palregs[i] = temp;
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}
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}
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}
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////////////////////////////////////////////////////////////////////////
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//
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// Machine dependent functions
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//
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void
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AlphaISA::initCPU(ExecContext *xc, int cpuId)
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{
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initIPRs(xc, cpuId);
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// CPU comes up with PAL regs enabled
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swap_palshadow(regs, true);
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xc->setIntReg(16, cpuId);
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xc->setIntReg(0, cpuId);
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xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + fault_addr(ResetFault));
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xc->setNextPC(xc->readPC() + sizeof(MachInst));
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}
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////////////////////////////////////////////////////////////////////////
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//
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// alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
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//
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const Addr
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AlphaISA::fault_addr(Fault fault)
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{
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//Check for the system wide faults
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if(fault == NoFault) return 0x0000;
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else if(fault == MachineCheckFault) return 0x0401;
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else if(fault == AlignmentFault) return 0x0301;
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//Deal with the alpha specific faults
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return ((AlphaFault*)fault)->vect;
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};
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const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
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/* 0 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 8 */ 1, 1, 1, 1, 1, 1, 1, 0,
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/* 16 */ 0, 0, 0, 0, 0, 0, 0, 0,
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/* 24 */ 0, 1, 0, 0, 0, 0, 0, 0 };
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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void
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AlphaISA::initIPRs(ExecContext *xc, int cpuId)
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{
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for (int i = 0; i < NumInternalProcRegs; ++i) {
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xc->setMiscReg(i, 0);
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}
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xc->setMiscReg(IPR_PAL_BASE, PalBase);
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xc->setMiscReg(IPR_MCSR, 0x6);
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xc->setMiscReg(IPR_PALtemp16, cpuId);
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}
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template <class CPU>
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void
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AlphaISA::processInterrupts(CPU *cpu)
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{
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//Check if there are any outstanding interrupts
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//Handle the interrupts
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int ipl = 0;
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int summary = 0;
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cpu->checkInterrupts = false;
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if (cpu->readMiscReg(IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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if (cpu->readMiscReg(IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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}
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}
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}
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uint64_t interrupts = cpu->intr_status();
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if (interrupts) {
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for (int i = INTLEVEL_EXTERNAL_MIN;
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i < INTLEVEL_EXTERNAL_MAX; i++) {
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if (interrupts & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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ipl = i;
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summary |= (ULL(1) << i);
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}
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}
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}
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if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
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cpu->setMiscReg(IPR_ISR, summary);
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cpu->setMiscReg(IPR_INTID, ipl);
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cpu->trap(InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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cpu->readMiscReg(IPR_IPLR), ipl, summary);
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}
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}
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template <class CPU>
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void
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AlphaISA::zeroRegisters(CPU *cpu)
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{
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// Insure ISA semantics
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// (no longer very clean due to the change in setIntReg() in the
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// cpu model. Consider changing later.)
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cpu->cpuXC->setIntReg(ZeroReg, 0);
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cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
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}
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void
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CPUExecContext::ev5_trap(Fault fault)
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{
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DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
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cpu->recordEvent(csprintf("Fault %s", fault->name));
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assert(!misspeculating());
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cpu->kernelStats->fault(fault);
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if (fault == ArithmeticFault)
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panic("Arithmetic traps are unimplemented!");
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// exception restart address
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if (fault != InterruptFault || !inPalMode())
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setMiscReg(AlphaISA::IPR_EXC_ADDR, regs.pc);
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if (fault == PalFault || fault == ArithmeticFault /* ||
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fault == InterruptFault && !inPalMode() */) {
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// traps... skip faulting instruction
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setMiscReg(AlphaISA::IPR_EXC_ADDR,
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readMiscReg(AlphaISA::IPR_EXC_ADDR) + 4);
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}
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if (!inPalMode())
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AlphaISA::swap_palshadow(®s, true);
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regs.pc = readMiscReg(AlphaISA::IPR_PAL_BASE) + AlphaISA::fault_addr(fault);
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regs.npc = regs.pc + sizeof(MachInst);
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}
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void
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AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
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{
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bool use_pc = (fault == NoFault);
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if (fault == ArithmeticFault)
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panic("arithmetic faults NYI...");
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// compute exception restart address
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if (use_pc || fault == PalFault || fault == ArithmeticFault) {
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// traps... skip faulting instruction
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc + 4);
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} else {
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// fault, post fault at excepting instruction
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regs->miscRegs.setReg(IPR_EXC_ADDR, regs->pc);
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}
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// jump to expection address (PAL PC bit set here as well...)
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if (!use_pc)
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) +
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fault_addr(fault);
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else
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regs->npc = regs->miscRegs.readReg(IPR_PAL_BASE) + pc;
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// that's it! (orders of magnitude less painful than x86)
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}
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Fault
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CPUExecContext::hwrei()
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{
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if (!inPalMode())
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return UnimplementedOpcodeFault;
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setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
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if (!misspeculating()) {
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cpu->kernelStats->hwrei();
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if ((readMiscReg(AlphaISA::IPR_EXC_ADDR) & 1) == 0)
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AlphaISA::swap_palshadow(®s, false);
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cpu->checkInterrupts = true;
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}
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// FIXME: XXX check for interrupts? XXX
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return NoFault;
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}
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AlphaISA::MiscReg
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AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
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{
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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// no side-effect
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= xc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
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break;
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case AlphaISA::IPR_VA:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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retval = ipr[idx];
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break;
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case AlphaISA::IPR_DTB_PTE:
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{
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AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
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retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
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retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
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retval |= ((u_int64_t)pte.xwe & ULL(0xf)) << 12;
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retval |= ((u_int64_t)pte.fonr & ULL(0x1)) << 1;
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retval |= ((u_int64_t)pte.fonw & ULL(0x1))<< 2;
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retval |= ((u_int64_t)pte.asma & ULL(0x1)) << 4;
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retval |= ((u_int64_t)pte.asn & ULL(0x7f)) << 57;
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}
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break;
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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fault = UnimplementedOpcodeFault;
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break;
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default:
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// invalid IPR
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fault = UnimplementedOpcodeFault;
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break;
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}
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return retval;
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}
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#ifdef DEBUG
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// Cause the simulator to break when changing to the following IPL
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int break_ipl = -1;
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#endif
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Fault
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AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
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{
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uint64_t old;
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if (xc->misspeculating())
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return NoFault;
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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break;
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case AlphaISA::IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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break;
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|
|
|
case AlphaISA::IPR_CC:
|
|
// This IPR only writes the upper 64 bits. It's ok to write
|
|
// all 64 here since we mask out the lower 32 in rpcc (see
|
|
// isa_desc).
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_PALtemp23:
|
|
// write entire quad w/ no side-effect
|
|
old = ipr[idx];
|
|
ipr[idx] = val;
|
|
xc->getCpuPtr()->kernelStats->context(old, val, xc);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_PTE:
|
|
// write entire quad w/ no side-effect, tag is forthcoming
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_ADDR:
|
|
// second least significant bit in PC is always zero
|
|
ipr[idx] = val & ~2;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ASTRR:
|
|
case AlphaISA::IPR_ASTER:
|
|
// only write least significant four bits - privilege mask
|
|
ipr[idx] = val & 0xf;
|
|
break;
|
|
|
|
case AlphaISA::IPR_IPLR:
|
|
#ifdef DEBUG
|
|
if (break_ipl != -1 && break_ipl == (val & 0x1f))
|
|
debug_break();
|
|
#endif
|
|
|
|
// only write least significant five bits - interrupt level
|
|
ipr[idx] = val & 0x1f;
|
|
xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_CM:
|
|
if (val & 0x18)
|
|
xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
|
|
else
|
|
xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
|
|
|
|
case AlphaISA::IPR_ICM:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ALT_MODE:
|
|
// only write two mode bits - processor mode
|
|
ipr[idx] = val & 0x18;
|
|
break;
|
|
|
|
case AlphaISA::IPR_MCSR:
|
|
// more here after optimization...
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_SIRR:
|
|
// only write software interrupt mask
|
|
ipr[idx] = val & 0x7fff0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ICSR:
|
|
ipr[idx] = val & ULL(0xffffff0300);
|
|
break;
|
|
|
|
case AlphaISA::IPR_IVPTBR:
|
|
case AlphaISA::IPR_MVPTBR:
|
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_TEST_CTL:
|
|
ipr[idx] = val & 0x1ffb;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DC_MODE:
|
|
case AlphaISA::IPR_MAF_MODE:
|
|
ipr[idx] = val & 0x3f;
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_ASN:
|
|
ipr[idx] = val & 0x7f0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_ASN:
|
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
|
break;
|
|
|
|
case AlphaISA::IPR_EXC_SUM:
|
|
case AlphaISA::IPR_EXC_MASK:
|
|
// any write to this register clears it
|
|
ipr[idx] = 0;
|
|
break;
|
|
|
|
case AlphaISA::IPR_INTID:
|
|
case AlphaISA::IPR_SL_RCV:
|
|
case AlphaISA::IPR_MM_STAT:
|
|
case AlphaISA::IPR_ITB_PTE_TEMP:
|
|
case AlphaISA::IPR_DTB_PTE_TEMP:
|
|
// read-only registers
|
|
return UnimplementedOpcodeFault;
|
|
|
|
case AlphaISA::IPR_HWINT_CLR:
|
|
case AlphaISA::IPR_SL_XMIT:
|
|
case AlphaISA::IPR_DC_FLUSH:
|
|
case AlphaISA::IPR_IC_FLUSH:
|
|
// the following are write only
|
|
ipr[idx] = val;
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->getDTBPtr()->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->getDTBPtr()->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
xc->getDTBPtr()->flushAddr(val,
|
|
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
|
break;
|
|
|
|
case AlphaISA::IPR_DTB_TAG: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
|
|
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
xc->getDTBPtr()->insert(val, pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_PTE: {
|
|
struct AlphaISA::PTE pte;
|
|
|
|
// FIXME: granularity hints NYI...
|
|
if (ITB_PTE_GH(val) != 0)
|
|
panic("PTE GH field != 0");
|
|
|
|
// write entire quad
|
|
ipr[idx] = val;
|
|
|
|
// construct PTE for new entry
|
|
pte.ppn = ITB_PTE_PPN(val);
|
|
pte.xre = ITB_PTE_XRE(val);
|
|
pte.xwe = 0;
|
|
pte.fonr = ITB_PTE_FONR(val);
|
|
pte.fonw = ITB_PTE_FONW(val);
|
|
pte.asma = ITB_PTE_ASMA(val);
|
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
|
|
|
// insert new TAG/PTE value into data TLB
|
|
xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
|
}
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IA:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->getITBPtr()->flushAll();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IAP:
|
|
// really a control write
|
|
ipr[idx] = 0;
|
|
|
|
xc->getITBPtr()->flushProcesses();
|
|
break;
|
|
|
|
case AlphaISA::IPR_ITB_IS:
|
|
// really a control write
|
|
ipr[idx] = val;
|
|
|
|
xc->getITBPtr()->flushAddr(val,
|
|
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
|
break;
|
|
|
|
default:
|
|
// invalid IPR
|
|
return UnimplementedOpcodeFault;
|
|
}
|
|
|
|
// no error...
|
|
return NoFault;
|
|
}
|
|
|
|
/**
|
|
* Check for special simulator handling of specific PAL calls.
|
|
* If return value is false, actual PAL call will be suppressed.
|
|
*/
|
|
bool
|
|
CPUExecContext::simPalCheck(int palFunc)
|
|
{
|
|
cpu->kernelStats->callpal(palFunc, proxy);
|
|
|
|
switch (palFunc) {
|
|
case PAL::halt:
|
|
halt();
|
|
if (--System::numSystemsRunning == 0)
|
|
new SimExitEvent("all cpus halted");
|
|
break;
|
|
|
|
case PAL::bpt:
|
|
case PAL::bugchk:
|
|
if (system->breakpoint())
|
|
return false;
|
|
break;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::processInterrupts(FastCPU *xc);
|
|
|
|
//Forward instantiation for FastCPU object
|
|
template
|
|
void AlphaISA::zeroRegisters(FastCPU *xc);
|
|
|
|
#endif // FULL_SYSTEM
|