5a1eb9049d
Can now serialize & unserialize DmaRequestEvents and DmaTransferEvents.
Also support serialize/unserialize of pointers to SimObjects and
other Serializable objects.
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/isa_traits.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/console.cc:
dev/console.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
cpu/simple_cpu/simple_cpu.cc:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Put ExecContext in its own section so its _status fields doesn't conflict.
sim/eventq.cc:
sim/eventq.hh:
unserialize() now takes a Checkpoint* instead of an IniFile*.
Events get serialized by the event queue only if they're marked
as AutoSerialize... others are assumed to be serialized by something
else (e.g. an owning SimObject) or to not matter.
sim/param.cc:
Shift 'const' in case T is a ptr type.
sim/serialize.cc:
sim/serialize.hh:
Define Checkpoint object to encapsulate everything you need to know
about a checkpoint. Use it to allow lookups of named Serializable
objects (and SimObjects) during unserialization.
unserialize() now takes a Checkpoint* instead of an IniFile*.
--HG--
extra : convert_revision : 8e6baab32405f8f548bb67a097b2f713296537a5
262 lines
8 KiB
C++
262 lines
8 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* System Console Definition
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*/
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#include <cstddef>
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#include <cstdio>
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#include <string>
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#include "base/inifile.hh"
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#include "base/str.hh" // for to_number()
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#include "base/trace.hh"
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#include "cpu/base_cpu.hh"
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#include "cpu/exec_context.hh"
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#include "dev/alpha_console.hh"
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#include "dev/console.hh"
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#include "dev/simple_disk.hh"
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#include "dev/tlaser_clock.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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AlphaConsole::AlphaConsole(const string &name, SimConsole *cons,
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SimpleDisk *d, int size, System *system,
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BaseCPU *cpu, TlaserClock *clock, int num_cpus,
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Addr addr, Addr mask, MemoryController *mmu)
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: MmapDevice(name, addr, mask, mmu), disk(d), console(cons)
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{
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consoleData = new uint8_t[size];
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memset(consoleData, 0, size);
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alphaAccess->last_offset = size - 1;
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alphaAccess->kernStart = system->getKernelStart();
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alphaAccess->kernEnd = system->getKernelEnd();
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alphaAccess->entryPoint = system->getKernelEntry();
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alphaAccess->version = ALPHA_ACCESS_VERSION;
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alphaAccess->numCPUs = num_cpus;
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alphaAccess->mem_size = system->physmem->getSize();
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alphaAccess->cpuClock = cpu->getFreq() / 1000000;
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alphaAccess->intrClockFrequency = clock->frequency();
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alphaAccess->diskUnit = 1;
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}
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Fault
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AlphaConsole::read(MemReqPtr req, uint8_t *data)
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{
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memset(data, 0, req->size);
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if (req->size == sizeof(uint32_t)) {
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Addr daddr = req->paddr & addr_mask;
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*(uint32_t *)data = *(uint32_t *)(consoleData + daddr);
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#if 0
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DPRINTF(AlphaConsole, "read: offset=%#x val=%#x\n",
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daddr, *(uint32_t *)data);
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#endif
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}
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return No_Fault;
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}
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Fault
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AlphaConsole::write(MemReqPtr req, const uint8_t *data)
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{
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uint64_t val;
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switch (req->size) {
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case sizeof(uint32_t):
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val = *(uint32_t *)data;
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break;
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case sizeof(uint64_t):
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val = *(uint64_t *)data;
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break;
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default:
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return Machine_Check_Fault;
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}
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Addr paddr = req->paddr & addr_mask;
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if (paddr == offsetof(AlphaAccess, diskUnit)) {
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alphaAccess->diskUnit = val;
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, diskCount)) {
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alphaAccess->diskCount = val;
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, diskPAddr)) {
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alphaAccess->diskPAddr = val;
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, diskBlock)) {
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alphaAccess->diskBlock = val;
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, diskOperation)) {
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if (val == 0x13)
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disk->read(alphaAccess->diskPAddr, alphaAccess->diskBlock,
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alphaAccess->diskCount);
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else
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panic("Invalid disk operation!");
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, outputChar)) {
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console->out((char)(val & 0xff), false);
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, bootStrapImpure)) {
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alphaAccess->bootStrapImpure = val;
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return No_Fault;
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}
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if (paddr == offsetof(AlphaAccess, bootStrapCPU)) {
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warn("%d: Trying to launch another CPU!", curTick);
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int cpu = val;
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assert(cpu > 0 && "Must not access primary cpu");
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ExecContext *other_xc = req->xc->system->execContexts[cpu];
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other_xc->regs.intRegFile[16] = cpu;
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other_xc->regs.ipr[TheISA::IPR_PALtemp16] = cpu;
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other_xc->regs.intRegFile[0] = cpu;
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other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
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other_xc->setStatus(ExecContext::Active); //Start the cpu
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return No_Fault;
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}
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return No_Fault;
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}
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void
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AlphaAccess::serialize(ostream &os)
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{
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SERIALIZE_SCALAR(last_offset);
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SERIALIZE_SCALAR(version);
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SERIALIZE_SCALAR(numCPUs);
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SERIALIZE_SCALAR(mem_size);
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SERIALIZE_SCALAR(cpuClock);
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SERIALIZE_SCALAR(intrClockFrequency);
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SERIALIZE_SCALAR(kernStart);
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SERIALIZE_SCALAR(kernEnd);
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SERIALIZE_SCALAR(entryPoint);
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SERIALIZE_SCALAR(diskUnit);
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SERIALIZE_SCALAR(diskCount);
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SERIALIZE_SCALAR(diskPAddr);
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SERIALIZE_SCALAR(diskBlock);
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SERIALIZE_SCALAR(diskOperation);
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SERIALIZE_SCALAR(outputChar);
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SERIALIZE_SCALAR(bootStrapImpure);
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SERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaAccess::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(last_offset);
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UNSERIALIZE_SCALAR(version);
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UNSERIALIZE_SCALAR(numCPUs);
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UNSERIALIZE_SCALAR(mem_size);
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UNSERIALIZE_SCALAR(cpuClock);
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UNSERIALIZE_SCALAR(intrClockFrequency);
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UNSERIALIZE_SCALAR(kernStart);
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UNSERIALIZE_SCALAR(kernEnd);
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UNSERIALIZE_SCALAR(entryPoint);
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UNSERIALIZE_SCALAR(diskUnit);
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UNSERIALIZE_SCALAR(diskCount);
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UNSERIALIZE_SCALAR(diskPAddr);
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UNSERIALIZE_SCALAR(diskBlock);
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UNSERIALIZE_SCALAR(diskOperation);
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UNSERIALIZE_SCALAR(outputChar);
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UNSERIALIZE_SCALAR(bootStrapImpure);
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UNSERIALIZE_SCALAR(bootStrapCPU);
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}
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void
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AlphaConsole::serialize(ostream &os)
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{
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alphaAccess->serialize(os);
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}
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void
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AlphaConsole::unserialize(Checkpoint *cp, const std::string §ion)
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{
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alphaAccess->unserialize(cp, section);
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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SimObjectParam<SimConsole *> sim_console;
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SimObjectParam<SimpleDisk *> disk;
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Param<int> size;
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Param<int> num_cpus;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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Param<Addr> mask;
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SimObjectParam<System *> system;
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SimObjectParam<BaseCPU *> cpu;
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SimObjectParam<TlaserClock *> clock;
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END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
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BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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INIT_PARAM(sim_console, "The Simulator Console"),
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INIT_PARAM(disk, "Simple Disk"),
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INIT_PARAM_DFLT(size, "AlphaConsole size", sizeof(AlphaAccess)),
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INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM(mask, "Address Mask"),
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INIT_PARAM(system, "system object"),
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INIT_PARAM(cpu, "Processor"),
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INIT_PARAM(clock, "Turbolaser Clock")
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END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
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CREATE_SIM_OBJECT(AlphaConsole)
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{
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return new AlphaConsole(getInstanceName(), sim_console,
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disk, size, system,
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cpu, clock, num_cpus,
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addr, mask, mmu);
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}
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REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)
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