e0b065ff7c
This makes testing a bit easier.
arch/alpha/alpha_memory.cc:
cpu/intr_control.cc:
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/alpha_console.cc:
dev/console.cc:
dev/disk_image.cc:
dev/etherbus.cc:
dev/etherdump.cc:
dev/etherlink.cc:
dev/ethertap.cc:
dev/simple_disk.cc:
kern/tru64/tru64_system.cc:
sim/main.cc:
sim/prog.cc:
Need to include builder.hh
sort #includes
sim/sim_object.cc:
sim/sim_object.hh:
Separate the SimObjectBuilder stuff into its own file
--HG--
extra : convert_revision : e8395e0cc6ae1f180f9cd6f100795a1ac44aeed5
60 lines
2.2 KiB
C++
60 lines
2.2 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include <vector>
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#include "cpu/base_cpu.hh"
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#include "cpu/intr_control.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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using namespace std;
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IntrControl::IntrControl(const string &name, BaseCPU *c)
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: SimObject(name), cpu(c)
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{}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
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SimObjectParam<BaseCPU *> cpu;
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END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
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BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
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INIT_PARAM(cpu, "the processor")
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END_INIT_SIM_OBJECT_PARAMS(IntrControl)
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CREATE_SIM_OBJECT(IntrControl)
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{
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return new IntrControl(getInstanceName(), cpu);
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}
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REGISTER_SIM_OBJECT("IntrControl", IntrControl)
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