313 lines
8.3 KiB
C++
313 lines
8.3 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __SIMPLE_CPU_HH__
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#define __SIMPLE_CPU_HH__
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#include "cpu/base_cpu.hh"
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#include "sim/eventq.hh"
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#include "base/loader/symtab.hh"
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#include "cpu/pc_event.hh"
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#include "base/statistics.hh"
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#include "cpu/exec_context.hh"
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// forward declarations
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#ifdef FULL_SYSTEM
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class Processor;
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class Kernel;
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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class MemInterface;
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class Checkpoint;
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namespace Trace {
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class InstRecord;
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}
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class SimpleCPU : public BaseCPU
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{
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public:
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// main simulation loop (one cycle)
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void tick();
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private:
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class TickEvent : public Event
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{
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private:
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SimpleCPU *cpu;
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public:
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TickEvent(SimpleCPU *c);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + delay);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + delay);
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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private:
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Trace::InstRecord *traceData;
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template<typename T>
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void trace_data(T data) {
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if (traceData) {
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traceData->setData(data);
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}
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};
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public:
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//
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enum Status {
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Running,
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Idle,
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IcacheMissStall,
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IcacheMissComplete,
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DcacheMissStall,
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SwitchedOut
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};
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private:
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Status _status;
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public:
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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#ifdef FULL_SYSTEM
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SimpleCPU(const std::string &_name,
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System *_system,
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Counter max_insts_any_thread, Counter max_insts_all_threads,
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Counter max_loads_any_thread, Counter max_loads_all_threads,
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AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
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MemInterface *icache_interface, MemInterface *dcache_interface,
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bool _def_reg, Tick freq);
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#else
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SimpleCPU(const std::string &_name, Process *_process,
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Counter max_insts_any_thread,
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Counter max_insts_all_threads,
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Counter max_loads_any_thread,
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Counter max_loads_all_threads,
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MemInterface *icache_interface, MemInterface *dcache_interface,
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bool _def_reg);
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#endif
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virtual ~SimpleCPU();
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virtual void init();
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// execution context
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ExecContext *xc;
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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#ifdef FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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#endif
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// L1 instruction cache
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MemInterface *icacheInterface;
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// L1 data cache
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MemInterface *dcacheInterface;
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bool defer_registration;
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// current instruction
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MachInst inst;
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// Refcounted pointer to the one memory request.
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MemReqPtr memReq;
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class CacheCompletionEvent : public Event
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{
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private:
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SimpleCPU *cpu;
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public:
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CacheCompletionEvent(SimpleCPU *_cpu);
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virtual void process();
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virtual const char *description();
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};
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CacheCompletionEvent cacheCompletionEvent;
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Status status() const { return _status; }
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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Stats::Scalar<> numInsts;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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// number of simulated memory references
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Stats::Scalar<> numMemRefs;
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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// number of cycles stalled for I-cache misses
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Stats::Scalar<> icacheStallCycles;
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Counter lastIcacheStall;
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// number of cycles stalled for D-cache misses
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Stats::Scalar<> dcacheStallCycles;
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Counter lastDcacheStall;
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void processCacheCompletion();
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res);
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); }
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float readFloatRegSingle(int reg_idx)
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{ return xc->readFloatRegSingle(reg_idx); }
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double readFloatRegDouble(int reg_idx)
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{ return xc->readFloatRegDouble(reg_idx); }
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uint64_t readFloatRegInt(int reg_idx)
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{ return xc->readFloatRegInt(reg_idx); }
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void setIntReg(int reg_idx, uint64_t val)
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{ return xc->setIntReg(reg_idx, val); }
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void setFloatRegSingle(int reg_idx, float val)
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{ return xc->setFloatRegSingle(reg_idx, val); }
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void setFloatRegDouble(int reg_idx, double val)
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{ return xc->setFloatRegDouble(reg_idx, val); }
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void setFloatRegInt(int reg_idx, uint64_t val)
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{ return xc->setFloatRegInt(reg_idx, val); }
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uint64_t readPC() { return xc->readPC(); }
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void setNextPC(uint64_t val) { return xc->setNextPC(val); }
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uint64_t readUniq() { return xc->readUniq(); }
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void setUniq(uint64_t val) { return xc->setUniq(val); }
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uint64_t readFpcr() { return xc->readFpcr(); }
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void setFpcr(uint64_t val) { return xc->setFpcr(val); }
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#ifdef FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
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Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
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Fault hwrei() { return xc->hwrei(); }
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int readIntrFlag() { return xc->readIntrFlag(); }
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void setIntrFlag(int val) { xc->setIntrFlag(val); }
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bool inPalMode() { return xc->inPalMode(); }
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void ev5_trap(Fault fault) { return xc->ev5_trap(fault); }
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bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
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#else
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void syscall() { xc->syscall(); }
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#endif
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bool misspeculating() { return xc->misspeculating(); }
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ExecContext *xcBase() { return xc; }
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};
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#endif // __SIMPLE_CPU_HH__
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