f05cb84ed1
This patch adds a connector that allows gem5 to be used as a component in SST (Structural Simulation Toolkit, sst-simulator.org). At a high level, this allows memory traffic to pass between the two simulators. SST Links are roughly analogous to gem5 Ports, although Links do not have a notion of master and slave. This distinction is important to gem5, so when connecting a gem5 CPU to an SST cache, an ExternalSlave must be used, and similarly when connecting the memory side of SST cache to a gem5 port (for memory <-> I/O), an ExternalMaster must be used. These connectors handle the administrative aspects of gem5 (initialization, simulation, shutdown) as well as translating SST's MemEvents into gem5 Packets and vice-versa.
120 lines
3.8 KiB
C++
120 lines
3.8 KiB
C++
// Copyright (c) 2015 ARM Limited
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// All rights reserved.
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// Copyright 2009-2014 Sandia Coporation. Under the terms
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// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
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// Government retains certain rights in this software.
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//
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// Copyright (c) 2009-2014, Sandia Corporation
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// All rights reserved.
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//
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// For license information, see the LICENSE file in the current directory.
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#ifndef EXT_SST_EXTSLAVE_HH
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#define EXT_SST_EXTSLAVE_HH
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#include <sst/core/serialization.h>
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#include <sst/core/component.h>
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#include <sst/core/output.h>
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#include <sst/core/interfaces/simpleMem.h>
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#include <sim/sim_object.hh>
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#include <mem/packet.hh>
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#include <mem/request.hh>
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#include <mem/external_slave.hh>
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namespace SST {
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class Link;
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class Event;
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class MemEvent;
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namespace gem5 {
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class gem5Component;
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class ExtSlave : public ExternalSlave::Port {
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public:
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const std::string name;
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bool
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recvTimingSnoopResp(PacketPtr packet)
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{
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fatal("recvTimingSnoopResp unimplemented");
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return false;
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}
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bool recvTimingReq(PacketPtr packet);
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void recvFunctional(PacketPtr packet);
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void recvRespRetry();
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Tick
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recvAtomic(PacketPtr packet)
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{
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fatal("recvAtomic unimplemented");
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}
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enum Phase { CONSTRUCTION, INIT, RUN };
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gem5Component *comp;
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Output &out;
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Phase simPhase;
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std::list<MemEvent*>* initPackets;
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Link* link;
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std::list<PacketPtr> respQ;
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bool blocked() { return !respQ.empty(); }
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typedef std::map<Event::id_type, ::Packet*> PacketMap_t;
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PacketMap_t PacketMap; // SST Event id -> gem5 Packet*
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public:
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ExtSlave(gem5Component*, Output&, ExternalSlave&, std::string&);
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void init(unsigned phase);
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void
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setup()
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{
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simPhase = RUN;
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}
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void handleEvent(Event*);
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};
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}
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}
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#endif
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