115 lines
3.5 KiB
C++
115 lines
3.5 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef CPU_INORDER_REG_DEP_MAP_HH
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#define CPU_INORDER_REG_DEP_MAP_HH
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#include <list>
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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class InOrderCPU;
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class RegDepMap
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{
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typedef ThePipeline::DynInstPtr DynInstPtr;
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public:
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RegDepMap(int size = TheISA::TotalNumRegs);
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~RegDepMap() { }
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std::string name();
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void setCPU(InOrderCPU *_cpu);
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/** Clear the Entire Map */
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void clear();
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/** Insert all of a instruction's destination registers into map*/
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void insert(DynInstPtr inst);
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/** Insert an instruction into a specific destination register index
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* onto map
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*/
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void insert(unsigned idx, DynInstPtr inst);
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/** Remove all of a instruction's destination registers into map*/
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void remove(DynInstPtr inst);
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/** Remove a specific instruction and dest. register index from map*/
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void remove(unsigned idx, DynInstPtr inst);
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/** Remove Front instruction from a destination register */
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void removeFront(unsigned idx, DynInstPtr inst);
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/** Is the current instruction able to read from this
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* destination register?
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*/
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bool canRead(unsigned idx, DynInstPtr inst);
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/** Is the current instruction able to get a forwarded value from
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* another instruction for this destination register?
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*/
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DynInstPtr canForward(unsigned reg_idx, DynInstPtr inst);
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/** find an instruction to forward/bypass a value from */
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DynInstPtr findBypassInst(unsigned idx);
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/** Is the current instruction able to write to this
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* destination register?
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*/
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bool canWrite(unsigned idx, DynInstPtr inst);
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/** Size of Dependency of Map */
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int depSize(unsigned idx);
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void dump();
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protected:
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// Eventually make this a map of lists for
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// efficiency sake!
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std::vector<std::list<DynInstPtr> > regMap;
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InOrderCPU *cpu;
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};
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#endif
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