8e4ec55703
arch/alpha/arguments.cc:
Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
Replaced setFloatRegDouble with setFloatReg
--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
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|---|---|---|
| .. | ||
| memtest | ||
| o3 | ||
| ozone | ||
| simple | ||
| trace | ||
| base.cc | ||
| base.hh | ||
| base_dyn_inst.cc | ||
| base_dyn_inst.hh | ||
| cpu_exec_context.cc | ||
| cpu_exec_context.hh | ||
| cpu_models.py | ||
| exec_context.hh | ||
| exetrace.cc | ||
| exetrace.hh | ||
| inst_seq.hh | ||
| intr_control.cc | ||
| intr_control.hh | ||
| op_class.cc | ||
| op_class.hh | ||
| pc_event.cc | ||
| pc_event.hh | ||
| profile.cc | ||
| profile.hh | ||
| SConscript | ||
| smt.hh | ||
| static_inst.cc | ||
| static_inst.hh | ||