ad8b9636f8
Update copyright dates and author list
SConscript:
arch/alpha/alpha_linux_process.cc:
arch/alpha/alpha_linux_process.hh:
arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
arch/alpha/alpha_tru64_process.cc:
arch/alpha/alpha_tru64_process.hh:
arch/alpha/aout_machdep.h:
arch/alpha/arguments.cc:
arch/alpha/arguments.hh:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/faults.cc:
arch/alpha/faults.hh:
arch/alpha/isa_desc:
arch/alpha/isa_traits.hh:
arch/alpha/osfpal.cc:
arch/alpha/osfpal.hh:
arch/alpha/pseudo_inst.cc:
arch/alpha/pseudo_inst.hh:
arch/alpha/vptr.hh:
arch/alpha/vtophys.cc:
arch/alpha/vtophys.hh:
base/bitfield.hh:
base/callback.hh:
base/circlebuf.cc:
base/circlebuf.hh:
base/cprintf.cc:
base/cprintf.hh:
base/cprintf_formats.hh:
base/crc.hh:
base/date.cc:
base/dbl_list.hh:
base/endian.hh:
base/fast_alloc.cc:
base/fast_alloc.hh:
base/fifo_buffer.cc:
base/fifo_buffer.hh:
base/hashmap.hh:
base/hostinfo.cc:
base/hostinfo.hh:
base/hybrid_pred.cc:
base/hybrid_pred.hh:
base/inet.cc:
base/inet.hh:
base/inifile.cc:
base/inifile.hh:
base/intmath.cc:
base/intmath.hh:
base/match.cc:
base/match.hh:
base/misc.cc:
base/misc.hh:
base/mod_num.hh:
base/mysql.cc:
base/mysql.hh:
base/output.cc:
base/output.hh:
base/pollevent.cc:
base/pollevent.hh:
base/predictor.hh:
base/random.cc:
base/random.hh:
base/range.cc:
base/range.hh:
base/refcnt.hh:
base/remote_gdb.cc:
base/remote_gdb.hh:
base/res_list.hh:
base/sat_counter.cc:
base/sat_counter.hh:
base/sched_list.hh:
base/socket.cc:
base/socket.hh:
base/statistics.cc:
base/statistics.hh:
base/compression/lzss_compression.cc:
base/compression/lzss_compression.hh:
base/compression/null_compression.hh:
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.cc:
base/loader/object_file.hh:
base/loader/symtab.cc:
base/loader/symtab.hh:
base/stats/events.cc:
base/stats/events.hh:
base/stats/flags.hh:
base/stats/mysql.cc:
base/stats/mysql.hh:
base/stats/mysql_run.hh:
base/stats/output.hh:
base/stats/statdb.cc:
base/stats/statdb.hh:
base/stats/text.cc:
base/stats/text.hh:
base/stats/types.hh:
base/stats/visit.cc:
base/stats/visit.hh:
base/str.cc:
base/str.hh:
base/time.cc:
base/time.hh:
base/timebuf.hh:
base/trace.cc:
base/trace.hh:
base/userinfo.cc:
base/userinfo.hh:
build/SConstruct:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/exetrace.cc:
cpu/exetrace.hh:
cpu/inst_seq.hh:
cpu/intr_control.cc:
cpu/intr_control.hh:
cpu/memtest/memtest.cc:
cpu/pc_event.cc:
cpu/pc_event.hh:
cpu/smt.hh:
cpu/static_inst.cc:
cpu/static_inst.hh:
cpu/memtest/memtest.hh:
cpu/o3/sat_counter.cc:
cpu/o3/sat_counter.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/ibm_reader.cc:
cpu/trace/reader/ibm_reader.hh:
cpu/trace/reader/itx_reader.cc:
cpu/trace/reader/itx_reader.hh:
cpu/trace/reader/m5_reader.cc:
cpu/trace/reader/m5_reader.hh:
cpu/trace/reader/mem_trace_reader.cc:
cpu/trace/reader/mem_trace_reader.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
dev/alpha_access.h:
dev/alpha_console.cc:
dev/alpha_console.hh:
dev/baddev.cc:
dev/baddev.hh:
dev/disk_image.cc:
dev/disk_image.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.cc:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/io_device.cc:
dev/io_device.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/ns_gige_reg.h:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/pcidev.cc:
dev/pcidev.hh:
dev/pcireg.h:
dev/pktfifo.cc:
dev/pktfifo.hh:
dev/platform.cc:
dev/platform.hh:
dev/simconsole.cc:
dev/simconsole.hh:
dev/simple_disk.cc:
dev/simple_disk.hh:
dev/sinic.cc:
dev/sinic.hh:
dev/sinicreg.hh:
dev/tsunami.cc:
dev/tsunami.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunamireg.h:
dev/uart.cc:
dev/uart.hh:
dev/uart8250.cc:
dev/uart8250.hh:
docs/stl.hh:
encumbered/cpu/full/op_class.hh:
kern/kernel_stats.cc:
kern/kernel_stats.hh:
kern/linux/linux.hh:
kern/linux/linux_syscalls.cc:
kern/linux/linux_syscalls.hh:
kern/linux/linux_system.cc:
kern/linux/linux_system.hh:
kern/linux/linux_threadinfo.hh:
kern/linux/printk.cc:
kern/linux/printk.hh:
kern/system_events.cc:
kern/system_events.hh:
kern/tru64/dump_mbuf.cc:
kern/tru64/dump_mbuf.hh:
kern/tru64/mbuf.hh:
kern/tru64/printf.cc:
kern/tru64/printf.hh:
kern/tru64/tru64.hh:
kern/tru64/tru64_events.cc:
kern/tru64/tru64_events.hh:
kern/tru64/tru64_syscalls.cc:
kern/tru64/tru64_syscalls.hh:
kern/tru64/tru64_system.cc:
kern/tru64/tru64_system.hh:
python/SConscript:
python/m5/__init__.py:
python/m5/config.py:
python/m5/convert.py:
python/m5/multidict.py:
python/m5/smartdict.py:
sim/async.hh:
sim/builder.cc:
sim/builder.hh:
sim/debug.cc:
sim/debug.hh:
sim/eventq.cc:
sim/eventq.hh:
sim/host.hh:
sim/main.cc:
sim/param.cc:
sim/param.hh:
sim/process.cc:
sim/process.hh:
sim/root.cc:
sim/serialize.cc:
sim/serialize.hh:
sim/sim_events.cc:
sim/sim_events.hh:
sim/sim_exit.hh:
sim/sim_object.cc:
sim/sim_object.hh:
sim/startup.cc:
sim/startup.hh:
sim/stat_control.cc:
sim/stat_control.hh:
sim/stats.hh:
sim/syscall_emul.cc:
sim/syscall_emul.hh:
sim/system.cc:
sim/system.hh:
test/bitvectest.cc:
test/circletest.cc:
test/cprintftest.cc:
test/genini.py:
test/initest.cc:
test/lru_test.cc:
test/nmtest.cc:
test/offtest.cc:
test/paramtest.cc:
test/rangetest.cc:
test/sized_test.cc:
test/stattest.cc:
test/strnumtest.cc:
test/symtest.cc:
test/tokentest.cc:
test/tracetest.cc:
util/ccdrv/devtime.c:
util/m5/m5.c:
util/oprofile-top.py:
util/rundiff:
util/m5/m5op.h:
util/m5/m5op.s:
util/stats/db.py:
util/stats/dbinit.py:
util/stats/display.py:
util/stats/info.py:
util/stats/print.py:
util/stats/stats.py:
util/tap/tap.cc:
Update copyright dates and author list
--HG--
extra : convert_revision : 0faba08fc0fc0146f1efb7f61e4b043c020ff9e4
326 lines
9.9 KiB
C
326 lines
9.9 KiB
C
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** @file
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* Ethernet device register definitions for the National
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* Semiconductor DP83820 Ethernet controller
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*/
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#ifndef __DEV_NS_GIGE_REG_H__
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#define __DEV_NS_GIGE_REG_H__
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/* Device Register Address Map */
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#define CR 0x00
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#define CFGR 0x04
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#define MEAR 0x08
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#define PTSCR 0x0c
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#define ISR 0x10
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#define IMR 0x14
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#define IER 0x18
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#define IHR 0x1c
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#define TXDP 0x20
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#define TXDP_HI 0x24
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#define TX_CFG 0x28
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#define GPIOR 0x2c
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#define RXDP 0x30
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#define RXDP_HI 0x34
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#define RX_CFG 0x38
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#define PQCR 0x3c
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#define WCSR 0x40
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#define PCR 0x44
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#define RFCR 0x48
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#define RFDR 0x4c
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#define BRAR 0x50
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#define BRDR 0x54
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#define SRR 0x58
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#define MIBC 0x5c
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#define MIB_START 0x60
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#define MIB_END 0x88
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#define VRCR 0xbc
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#define VTCR 0xc0
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#define VDR 0xc4
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#define CCSR 0xcc
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#define TBICR 0xe0
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#define TBISR 0xe4
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#define TANAR 0xe8
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#define TANLPAR 0xec
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#define TANER 0xf0
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#define TESR 0xf4
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#define M5REG 0xf8
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#define LAST 0xf8
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#define RESERVED 0xfc
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/* Chip Command Register */
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#define CR_TXE 0x00000001
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#define CR_TXD 0x00000002
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#define CR_RXE 0x00000004
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#define CR_RXD 0x00000008
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#define CR_TXR 0x00000010
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#define CR_RXR 0x00000020
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#define CR_SWI 0x00000080
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#define CR_RST 0x00000100
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/* configuration register */
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#define CFGR_LNKSTS 0x80000000
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#define CFGR_SPDSTS 0x60000000
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#define CFGR_SPDSTS1 0x40000000
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#define CFGR_SPDSTS0 0x20000000
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#define CFGR_DUPSTS 0x10000000
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#define CFGR_TBI_EN 0x01000000
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#define CFGR_RESERVED 0x0e000000
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#define CFGR_MODE_1000 0x00400000
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#define CFGR_AUTO_1000 0x00200000
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#define CFGR_PINT_CTL 0x001c0000
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#define CFGR_PINT_DUPSTS 0x00100000
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#define CFGR_PINT_LNKSTS 0x00080000
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#define CFGR_PINT_SPDSTS 0x00040000
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#define CFGR_TMRTEST 0x00020000
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#define CFGR_MRM_DIS 0x00010000
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#define CFGR_MWI_DIS 0x00008000
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#define CFGR_T64ADDR 0x00004000
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#define CFGR_PCI64_DET 0x00002000
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#define CFGR_DATA64_EN 0x00001000
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#define CFGR_M64ADDR 0x00000800
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#define CFGR_PHY_RST 0x00000400
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#define CFGR_PHY_DIS 0x00000200
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#define CFGR_EXTSTS_EN 0x00000100
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#define CFGR_REQALG 0x00000080
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#define CFGR_SB 0x00000040
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#define CFGR_POW 0x00000020
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#define CFGR_EXD 0x00000010
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#define CFGR_PESEL 0x00000008
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#define CFGR_BROM_DIS 0x00000004
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#define CFGR_EXT_125 0x00000002
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#define CFGR_BEM 0x00000001
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/* EEPROM access register */
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#define MEAR_EEDI 0x00000001
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#define MEAR_EEDO 0x00000002
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#define MEAR_EECLK 0x00000004
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#define MEAR_EESEL 0x00000008
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#define MEAR_MDIO 0x00000010
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#define MEAR_MDDIR 0x00000020
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#define MEAR_MDC 0x00000040
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/* PCI test control register */
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#define PTSCR_EEBIST_FAIL 0x00000001
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#define PTSCR_EEBIST_EN 0x00000002
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#define PTSCR_EELOAD_EN 0x00000004
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#define PTSCR_RBIST_FAIL 0x000001b8
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#define PTSCR_RBIST_DONE 0x00000200
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#define PTSCR_RBIST_EN 0x00000400
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#define PTSCR_RBIST_RST 0x00002000
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#define PTSCR_RBIST_RDONLY 0x000003f9
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/* interrupt status register */
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#define ISR_RESERVE 0x80000000
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#define ISR_TXDESC3 0x40000000
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#define ISR_TXDESC2 0x20000000
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#define ISR_TXDESC1 0x10000000
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#define ISR_TXDESC0 0x08000000
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#define ISR_RXDESC3 0x04000000
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#define ISR_RXDESC2 0x02000000
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#define ISR_RXDESC1 0x01000000
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#define ISR_RXDESC0 0x00800000
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#define ISR_TXRCMP 0x00400000
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#define ISR_RXRCMP 0x00200000
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#define ISR_DPERR 0x00100000
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#define ISR_SSERR 0x00080000
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#define ISR_RMABT 0x00040000
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#define ISR_RTABT 0x00020000
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#define ISR_RXSOVR 0x00010000
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#define ISR_HIBINT 0x00008000
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#define ISR_PHY 0x00004000
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#define ISR_PME 0x00002000
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#define ISR_SWI 0x00001000
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#define ISR_MIB 0x00000800
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#define ISR_TXURN 0x00000400
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#define ISR_TXIDLE 0x00000200
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#define ISR_TXERR 0x00000100
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#define ISR_TXDESC 0x00000080
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#define ISR_TXOK 0x00000040
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#define ISR_RXORN 0x00000020
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#define ISR_RXIDLE 0x00000010
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#define ISR_RXEARLY 0x00000008
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#define ISR_RXERR 0x00000004
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#define ISR_RXDESC 0x00000002
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#define ISR_RXOK 0x00000001
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#define ISR_ALL 0x7FFFFFFF
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#define ISR_NODELAY (ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC))
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#define ISR_NOIMPL (~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK))
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/* transmit configuration register */
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#define TX_CFG_CSI 0x80000000
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#define TX_CFG_HBI 0x40000000
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#define TX_CFG_MLB 0x20000000
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#define TX_CFG_ATP 0x10000000
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#define TX_CFG_ECRETRY 0x00800000
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#define TX_CFG_BRST_DIS 0x00080000
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#define TX_CFG_MXDMA1024 0x00000000
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#define TX_CFG_MXDMA512 0x00700000
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#define TX_CFG_MXDMA256 0x00600000
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#define TX_CFG_MXDMA128 0x00500000
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#define TX_CFG_MXDMA64 0x00400000
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#define TX_CFG_MXDMA32 0x00300000
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#define TX_CFG_MXDMA16 0x00200000
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#define TX_CFG_MXDMA8 0x00100000
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#define TX_CFG_MXDMA 0x00700000
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#define TX_CFG_FLTH_MASK 0x0000ff00
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#define TX_CFG_DRTH_MASK 0x000000ff
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/*general purpose I/O control register */
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#define GPIOR_GP5_OE 0x00000200
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#define GPIOR_GP4_OE 0x00000100
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#define GPIOR_GP3_OE 0x00000080
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#define GPIOR_GP2_OE 0x00000040
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#define GPIOR_GP1_OE 0x00000020
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#define GPIOR_GP3_OUT 0x00000004
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#define GPIOR_GP1_OUT 0x00000001
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/* receive configuration register */
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#define RX_CFG_AEP 0x80000000
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#define RX_CFG_ARP 0x40000000
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#define RX_CFG_STRIPCRC 0x20000000
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#define RX_CFG_RX_FD 0x10000000
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#define RX_CFG_ALP 0x08000000
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#define RX_CFG_AIRL 0x04000000
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#define RX_CFG_MXDMA512 0x00700000
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#define RX_CFG_MXDMA 0x00700000
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#define RX_CFG_DRTH 0x0000003e
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#define RX_CFG_DRTH0 0x00000002
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/* pause control status register */
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#define PCR_PSEN (1 << 31)
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#define PCR_PS_MCAST (1 << 30)
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#define PCR_PS_DA (1 << 29)
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#define PCR_STHI_8 (3 << 23)
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#define PCR_STLO_4 (1 << 23)
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#define PCR_FFHI_8K (3 << 21)
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#define PCR_FFLO_4K (1 << 21)
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#define PCR_PAUSE_CNT 0xFFFE
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/*receive filter/match control register */
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#define RFCR_RFEN 0x80000000
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#define RFCR_AAB 0x40000000
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#define RFCR_AAM 0x20000000
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#define RFCR_AAU 0x10000000
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#define RFCR_APM 0x08000000
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#define RFCR_APAT 0x07800000
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#define RFCR_APAT3 0x04000000
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#define RFCR_APAT2 0x02000000
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#define RFCR_APAT1 0x01000000
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#define RFCR_APAT0 0x00800000
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#define RFCR_AARP 0x00400000
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#define RFCR_MHEN 0x00200000
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#define RFCR_UHEN 0x00100000
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#define RFCR_ULM 0x00080000
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#define RFCR_RFADDR 0x000003ff
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/* receive filter/match data register */
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#define RFDR_BMASK 0x00030000
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#define RFDR_RFDATA0 0x000000ff
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#define RFDR_RFDATA1 0x0000ff00
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/* management information base control register */
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#define MIBC_MIBS 0x00000008
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#define MIBC_ACLR 0x00000004
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#define MIBC_FRZ 0x00000002
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#define MIBC_WRN 0x00000001
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/* VLAN/IP receive control register */
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#define VRCR_RUDPE 0x00000080
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#define VRCR_RTCPE 0x00000040
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#define VRCR_RIPE 0x00000020
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#define VRCR_IPEN 0x00000010
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#define VRCR_DUTF 0x00000008
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#define VRCR_DVTF 0x00000004
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#define VRCR_VTREN 0x00000002
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#define VRCR_VTDEN 0x00000001
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/* VLAN/IP transmit control register */
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#define VTCR_PPCHK 0x00000008
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#define VTCR_GCHK 0x00000004
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#define VTCR_VPPTI 0x00000002
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#define VTCR_VGTI 0x00000001
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/* Clockrun Control/Status Register */
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#define CCSR_CLKRUN_EN 0x00000001
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/* TBI control register */
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#define TBICR_MR_LOOPBACK 0x00004000
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#define TBICR_MR_AN_ENABLE 0x00001000
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#define TBICR_MR_RESTART_AN 0x00000200
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/* TBI status register */
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#define TBISR_MR_LINK_STATUS 0x00000020
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#define TBISR_MR_AN_COMPLETE 0x00000004
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/* TBI auto-negotiation advertisement register */
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#define TANAR_PS2 0x00000100
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#define TANAR_PS1 0x00000080
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#define TANAR_HALF_DUP 0x00000040
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#define TANAR_FULL_DUP 0x00000020
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/*
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* descriptor format currently assuming link and bufptr
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* are set for 32 bits,( may be wrong ) ASSUME32
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*/
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struct ns_desc {
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uint32_t link; /* link field to next descriptor in linked list */
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uint32_t bufptr; /* pointer to the first fragment or buffer */
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uint32_t cmdsts; /* command/status field */
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uint32_t extsts; /* extended status field for VLAN and IP info */
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};
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/* cmdsts flags for descriptors */
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#define CMDSTS_OWN 0x80000000
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#define CMDSTS_MORE 0x40000000
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#define CMDSTS_INTR 0x20000000
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#define CMDSTS_ERR 0x10000000
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#define CMDSTS_OK 0x08000000
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#define CMDSTS_LEN_MASK 0x0000ffff
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#define CMDSTS_DEST_MASK 0x01800000
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#define CMDSTS_DEST_SELF 0x00800000
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#define CMDSTS_DEST_MULTI 0x01000000
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/* extended flags for descriptors */
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#define EXTSTS_UDPERR 0x00400000
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#define EXTSTS_UDPPKT 0x00200000
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#define EXTSTS_TCPERR 0x00100000
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#define EXTSTS_TCPPKT 0x00080000
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#define EXTSTS_IPERR 0x00040000
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#define EXTSTS_IPPKT 0x00020000
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/* speed status */
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#define SPDSTS_POLARITY (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS | (lnksts ? CFGR_LNKSTS : 0))
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#endif /* __DEV_NS_GIGE_REG_H__ */
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