405 lines
11 KiB
C++
405 lines
11 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_INSTS_VFP_HH__
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#define __ARCH_ARM_INSTS_VFP_HH__
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#include "arch/arm/insts/misc.hh"
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#include "arch/arm/miscregs.hh"
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#include <fenv.h>
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enum VfpMicroMode {
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VfpNotAMicroop,
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VfpMicroop,
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VfpFirstMicroop,
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VfpLastMicroop
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};
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template<class T>
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static inline void
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setVfpMicroFlags(VfpMicroMode mode, T &flags)
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{
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switch (mode) {
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case VfpMicroop:
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flags[StaticInst::IsMicroop] = true;
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break;
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case VfpFirstMicroop:
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flags[StaticInst::IsMicroop] =
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flags[StaticInst::IsFirstMicroop] = true;
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break;
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case VfpLastMicroop:
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flags[StaticInst::IsMicroop] =
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flags[StaticInst::IsLastMicroop] = true;
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break;
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case VfpNotAMicroop:
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break;
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}
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if (mode == VfpMicroop || mode == VfpFirstMicroop) {
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flags[StaticInst::IsDelayedCommit] = true;
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}
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}
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enum FeExceptionBit
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{
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FeDivByZero = FE_DIVBYZERO,
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FeInexact = FE_INEXACT,
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FeInvalid = FE_INVALID,
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FeOverflow = FE_OVERFLOW,
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FeUnderflow = FE_UNDERFLOW,
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FeAllExceptions = FE_ALL_EXCEPT
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};
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enum FeRoundingMode
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{
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FeRoundDown = FE_DOWNWARD,
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FeRoundNearest = FE_TONEAREST,
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FeRoundZero = FE_TOWARDZERO,
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FeRoundUpward = FE_UPWARD
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};
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enum VfpRoundingMode
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{
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VfpRoundNearest = 0,
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VfpRoundUpward = 1,
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VfpRoundDown = 2,
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VfpRoundZero = 3
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};
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static inline uint64_t
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vfpFpSToFixed(float val, bool isSigned, bool half, uint8_t imm)
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{
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fesetround(FeRoundZero);
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val = val * powf(2.0, imm);
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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feclearexcept(FeAllExceptions);
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if (isSigned) {
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if (half) {
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if ((double)val < (int16_t)(1 << 15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)(1 << 15);
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}
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if ((double)val > (int16_t)mask(15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)mask(15);
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}
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return (int16_t)val;
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} else {
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if ((double)val < (int32_t)(1 << 31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)(1 << 31);
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}
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if ((double)val > (int32_t)mask(31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)mask(31);
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}
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return (int32_t)val;
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}
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} else {
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if (half) {
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if ((double)val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if ((double)val > (mask(16))) {
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feraiseexcept(FeInvalid);
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return mask(16);
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}
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return (uint16_t)val;
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} else {
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if ((double)val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if ((double)val > (mask(32))) {
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feraiseexcept(FeInvalid);
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return mask(32);
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}
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return (uint32_t)val;
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}
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}
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}
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static inline float
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vfpUFixedToFpS(uint32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = (uint16_t)val;
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return val / powf(2.0, imm);
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}
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static inline float
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vfpSFixedToFpS(int32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = sext<16>(val & mask(16));
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return val / powf(2.0, imm);
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}
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static inline uint64_t
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vfpFpDToFixed(double val, bool isSigned, bool half, uint8_t imm)
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{
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fesetround(FeRoundZero);
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val = val * pow(2.0, imm);
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__asm__ __volatile__("" : "=m" (val) : "m" (val));
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feclearexcept(FeAllExceptions);
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if (isSigned) {
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if (half) {
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if (val < (int16_t)(1 << 15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)(1 << 15);
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}
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if (val > (int16_t)mask(15)) {
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feraiseexcept(FeInvalid);
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return (int16_t)mask(15);
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}
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return (int16_t)val;
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} else {
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if (val < (int32_t)(1 << 31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)(1 << 31);
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}
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if (val > (int32_t)mask(31)) {
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feraiseexcept(FeInvalid);
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return (int32_t)mask(31);
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}
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return (int32_t)val;
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}
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} else {
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if (half) {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > mask(16)) {
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feraiseexcept(FeInvalid);
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return mask(16);
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}
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return (uint16_t)val;
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} else {
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if (val < 0) {
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feraiseexcept(FeInvalid);
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return 0;
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}
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if (val > mask(32)) {
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feraiseexcept(FeInvalid);
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return mask(32);
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}
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return (uint32_t)val;
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}
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}
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}
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static inline double
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vfpUFixedToFpD(uint32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = (uint16_t)val;
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return val / pow(2.0, imm);
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}
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static inline double
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vfpSFixedToFpD(int32_t val, bool half, uint8_t imm)
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{
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fesetround(FeRoundNearest);
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if (half)
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val = sext<16>(val & mask(16));
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return val / pow(2.0, imm);
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}
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typedef int VfpSavedState;
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static inline VfpSavedState
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prepVfpFpscr(FPSCR fpscr)
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{
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int roundingMode = fegetround();
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feclearexcept(FeAllExceptions);
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switch (fpscr.rMode) {
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case VfpRoundNearest:
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fesetround(FeRoundNearest);
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break;
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case VfpRoundUpward:
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fesetround(FeRoundUpward);
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break;
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case VfpRoundDown:
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fesetround(FeRoundDown);
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break;
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case VfpRoundZero:
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fesetround(FeRoundZero);
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break;
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}
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return roundingMode;
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}
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static inline FPSCR
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setVfpFpscr(FPSCR fpscr, VfpSavedState state)
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{
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int exceptions = fetestexcept(FeAllExceptions);
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if (exceptions & FeInvalid) {
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fpscr.ioc = 1;
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}
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if (exceptions & FeDivByZero) {
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fpscr.dzc = 1;
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}
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if (exceptions & FeOverflow) {
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fpscr.ofc = 1;
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}
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if (exceptions & FeUnderflow) {
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fpscr.ufc = 1;
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}
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if (exceptions & FeInexact) {
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fpscr.ixc = 1;
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}
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fesetround(state);
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return fpscr;
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}
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class VfpMacroOp : public PredMacroOp
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{
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public:
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static bool
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inScalarBank(IntRegIndex idx)
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{
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return (idx % 32) < 8;
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}
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protected:
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bool wide;
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VfpMacroOp(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, bool _wide) :
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PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
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{}
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IntRegIndex
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addStride(IntRegIndex idx, unsigned stride)
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{
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if (wide) {
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stride *= 2;
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}
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unsigned offset = idx % 8;
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idx = (IntRegIndex)(idx - offset);
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offset += stride;
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idx = (IntRegIndex)(idx + (offset % 8));
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return idx;
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}
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void
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nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
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{
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unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
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assert(!inScalarBank(dest));
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dest = addStride(dest, stride);
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op1 = addStride(op1, stride);
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if (!inScalarBank(op2)) {
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op2 = addStride(op2, stride);
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}
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}
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void
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nextIdxs(IntRegIndex &dest, IntRegIndex &op1)
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{
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unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
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assert(!inScalarBank(dest));
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dest = addStride(dest, stride);
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if (!inScalarBank(op1)) {
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op1 = addStride(op1, stride);
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}
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}
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void
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nextIdxs(IntRegIndex &dest)
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{
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unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
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assert(!inScalarBank(dest));
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dest = addStride(dest, stride);
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}
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};
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class VfpRegRegOp : public RegRegOp
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{
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protected:
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VfpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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VfpMicroMode mode = VfpNotAMicroop) :
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RegRegOp(mnem, _machInst, __opClass, _dest, _op1)
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{
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setVfpMicroFlags(mode, flags);
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}
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};
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class VfpRegImmOp : public RegImmOp
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{
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protected:
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VfpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, uint64_t _imm,
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VfpMicroMode mode = VfpNotAMicroop) :
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RegImmOp(mnem, _machInst, __opClass, _dest, _imm)
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{
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setVfpMicroFlags(mode, flags);
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}
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};
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class VfpRegRegImmOp : public RegRegImmOp
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{
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protected:
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VfpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1,
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uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
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RegRegImmOp(mnem, _machInst, __opClass, _dest, _op1, _imm)
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{
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setVfpMicroFlags(mode, flags);
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}
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};
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class VfpRegRegRegOp : public RegRegRegOp
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{
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protected:
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VfpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
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VfpMicroMode mode = VfpNotAMicroop) :
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RegRegRegOp(mnem, _machInst, __opClass, _dest, _op1, _op2)
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{
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setVfpMicroFlags(mode, flags);
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}
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};
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#endif //__ARCH_ARM_INSTS_VFP_HH__
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