21df09cf7a
cpu/base_dyn_inst.hh:
Remove snoop function (did not mean to commit it).
cpu/ozone/back_end_impl.hh:
Set instruction as having its result ready, not completed.
cpu/ozone/cpu.hh:
Fixes for store conditionals. Use an additional lock addr list to make sure that the access is valid. I don't know if this is fully necessary, but it gives me a peace of mind (at some performance cost).
Make sure to schedule for cycles(1) and not just 1 cycle in the future as tick = 1ps.
Also support the new Checker.
cpu/ozone/cpu_builder.cc:
Add parameter for maxOutstandingMemOps so it can be set through the config.
Also add in the checker. Right now it's a BaseCPU simobject, but that may change in the future.
cpu/ozone/cpu_impl.hh:
Add support for the checker. For now there's a dynamic cast to convert the simobject passed back from the builder to the proper Checker type. It's ugly, but only happens at startup, and is probably a justified use of dynamic cast.
Support switching out/taking over from other CPUs.
Correct indexing problem for float registers.
cpu/ozone/dyn_inst.hh:
Add ability for instructions to wait on memory instructions in addition to source register instructions. This is needed for memory dependence predictors and memory barriers.
cpu/ozone/dyn_inst_impl.hh:
Support waiting on memory operations.
Use "resultReady" to differentiate an instruction having its registers produced vs being totally completed.
cpu/ozone/front_end.hh:
Support switching out.
Also record if an interrupt is pending.
cpu/ozone/front_end_impl.hh:
Support switching out. Also support stalling the front end if an interrupt is pending.
cpu/ozone/lw_back_end.hh:
Add checker in.
Support switching out.
Support memory barriers.
cpu/ozone/lw_back_end_impl.hh:
Lots of changes to get things to work right.
Faults, traps, interrupts all wait until all stores have written back (important).
Memory barriers are supported, as is the general ability for instructions to be dependent on other memory instructions.
cpu/ozone/lw_lsq.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
cpu/ozone/lw_lsq_impl.hh:
Support switching out.
Also use store writeback events in all cases, not just dcache misses.
Support the checker CPU. Marks instructions as completed once the functional access is done (which has to be done for the checker to be able to verify results).
cpu/ozone/simple_params.hh:
Add max outstanding mem ops parameter.
python/m5/objects/OzoneCPU.py:
Add max outstanding mem ops, checker.
--HG--
extra : convert_revision : f4d408e1bb1f25836a097b6abe3856111e950c59
165 lines
3.3 KiB
C++
165 lines
3.3 KiB
C++
|
|
|
|
#ifndef __CPU_OZONE_SIMPLE_PARAMS_HH__
|
|
#define __CPU_OZONE_SIMPLE_PARAMS_HH__
|
|
|
|
#include "cpu/ozone/cpu.hh"
|
|
|
|
//Forward declarations
|
|
class AlphaDTB;
|
|
class AlphaITB;
|
|
class FUPool;
|
|
class FunctionalMemory;
|
|
class MemInterface;
|
|
class PageTable;
|
|
class Process;
|
|
class System;
|
|
|
|
/**
|
|
* This file defines the parameters that will be used for the OzoneCPU.
|
|
* This must be defined externally so that the Impl can have a params class
|
|
* defined that it can pass to all of the individual stages.
|
|
*/
|
|
|
|
class SimpleParams : public BaseCPU::Params
|
|
{
|
|
public:
|
|
|
|
#if FULL_SYSTEM
|
|
AlphaITB *itb; AlphaDTB *dtb;
|
|
#else
|
|
std::vector<Process *> workload;
|
|
// Process *process;
|
|
#endif // FULL_SYSTEM
|
|
|
|
//Page Table
|
|
PageTable *pTable;
|
|
|
|
FunctionalMemory *mem;
|
|
|
|
//
|
|
// Caches
|
|
//
|
|
MemInterface *icacheInterface;
|
|
MemInterface *dcacheInterface;
|
|
|
|
unsigned cachePorts;
|
|
unsigned width;
|
|
unsigned frontEndWidth;
|
|
unsigned backEndWidth;
|
|
unsigned backEndSquashLatency;
|
|
unsigned backEndLatency;
|
|
unsigned maxInstBufferSize;
|
|
unsigned numPhysicalRegs;
|
|
unsigned maxOutstandingMemOps;
|
|
//
|
|
// Fetch
|
|
//
|
|
unsigned decodeToFetchDelay;
|
|
unsigned renameToFetchDelay;
|
|
unsigned iewToFetchDelay;
|
|
unsigned commitToFetchDelay;
|
|
unsigned fetchWidth;
|
|
|
|
//
|
|
// Decode
|
|
//
|
|
unsigned renameToDecodeDelay;
|
|
unsigned iewToDecodeDelay;
|
|
unsigned commitToDecodeDelay;
|
|
unsigned fetchToDecodeDelay;
|
|
unsigned decodeWidth;
|
|
|
|
//
|
|
// Rename
|
|
//
|
|
unsigned iewToRenameDelay;
|
|
unsigned commitToRenameDelay;
|
|
unsigned decodeToRenameDelay;
|
|
unsigned renameWidth;
|
|
|
|
//
|
|
// IEW
|
|
//
|
|
unsigned commitToIEWDelay;
|
|
unsigned renameToIEWDelay;
|
|
unsigned issueToExecuteDelay;
|
|
unsigned issueWidth;
|
|
unsigned executeWidth;
|
|
unsigned executeIntWidth;
|
|
unsigned executeFloatWidth;
|
|
unsigned executeBranchWidth;
|
|
unsigned executeMemoryWidth;
|
|
FUPool *fuPool;
|
|
|
|
//
|
|
// Commit
|
|
//
|
|
unsigned iewToCommitDelay;
|
|
unsigned renameToROBDelay;
|
|
unsigned commitWidth;
|
|
unsigned squashWidth;
|
|
|
|
//
|
|
// Branch predictor (BP & BTB)
|
|
//
|
|
unsigned localPredictorSize;
|
|
unsigned localCtrBits;
|
|
unsigned localHistoryTableSize;
|
|
unsigned localHistoryBits;
|
|
unsigned globalPredictorSize;
|
|
unsigned globalCtrBits;
|
|
unsigned globalHistoryBits;
|
|
unsigned choicePredictorSize;
|
|
unsigned choiceCtrBits;
|
|
|
|
unsigned BTBEntries;
|
|
unsigned BTBTagSize;
|
|
|
|
unsigned RASSize;
|
|
|
|
//
|
|
// Load store queue
|
|
//
|
|
unsigned LQEntries;
|
|
unsigned SQEntries;
|
|
|
|
//
|
|
// Memory dependence
|
|
//
|
|
unsigned SSITSize;
|
|
unsigned LFSTSize;
|
|
|
|
//
|
|
// Miscellaneous
|
|
//
|
|
unsigned numPhysIntRegs;
|
|
unsigned numPhysFloatRegs;
|
|
unsigned numIQEntries;
|
|
unsigned numROBEntries;
|
|
|
|
bool decoupledFrontEnd;
|
|
int dispatchWidth;
|
|
int wbWidth;
|
|
|
|
//SMT Parameters
|
|
unsigned smtNumFetchingThreads;
|
|
|
|
std::string smtFetchPolicy;
|
|
|
|
std::string smtIQPolicy;
|
|
unsigned smtIQThreshold;
|
|
|
|
std::string smtLSQPolicy;
|
|
unsigned smtLSQThreshold;
|
|
|
|
std::string smtCommitPolicy;
|
|
|
|
std::string smtROBPolicy;
|
|
unsigned smtROBThreshold;
|
|
|
|
// Probably can get this from somewhere.
|
|
unsigned instShiftAmt;
|
|
};
|
|
|
|
#endif // __CPU_OZONE_SIMPLE_PARAMS_HH__
|