212 lines
7.4 KiB
C++
212 lines
7.4 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
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#define __ARCH_ARM_INSTS_STATICINST_HH__
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#include "base/trace.hh"
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#include "cpu/static_inst.hh"
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namespace ArmISA
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{
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class ArmStaticInst : public StaticInst
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{
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protected:
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int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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bool shift_carry_imm(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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bool shift_carry_rs(uint32_t base, uint32_t shamt,
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uint32_t type, uint32_t cfval) const;
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// Constructor
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ArmStaticInst(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: StaticInst(mnem, _machInst, __opClass)
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{
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}
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/// Print a register name for disassembly given the unique
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/// dependence tag number (FP or int).
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void printReg(std::ostream &os, int reg) const;
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void printMnemonic(std::ostream &os,
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const std::string &suffix = "",
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bool withPred = true) const;
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void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
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const std::string &prefix, const Addr addr,
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const std::string &suffix) const;
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void printShiftOperand(std::ostream &os, IntRegIndex rm,
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bool immShift, uint32_t shiftAmt,
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IntRegIndex rs, ArmShiftType type) const;
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void printDataInst(std::ostream &os, bool withImm) const;
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void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
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IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
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IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
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uint32_t imm) const;
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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static uint32_t
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cpsrWriteByInstr(CPSR cpsr, uint32_t val,
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uint8_t byteMask, bool affectState)
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{
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bool privileged = (cpsr.mode != MODE_USER);
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uint32_t bitMask = 0;
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if (bits(byteMask, 3)) {
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unsigned lowIdx = affectState ? 24 : 27;
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bitMask = bitMask | mask(31, lowIdx);
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}
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if (bits(byteMask, 2)) {
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bitMask = bitMask | mask(19, 16);
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}
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if (bits(byteMask, 1)) {
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unsigned highIdx = affectState ? 15 : 9;
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unsigned lowIdx = privileged ? 8 : 9;
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bitMask = bitMask | mask(highIdx, lowIdx);
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}
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if (bits(byteMask, 0)) {
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if (privileged) {
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bitMask = bitMask | mask(7, 6);
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bitMask = bitMask | mask(5);
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}
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if (affectState)
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bitMask = bitMask | (1 << 5);
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}
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return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
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}
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static uint32_t
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spsrWriteByInstr(uint32_t spsr, uint32_t val,
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uint8_t byteMask, bool affectState)
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{
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uint32_t bitMask = 0;
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if (bits(byteMask, 3))
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bitMask = bitMask | mask(31, 24);
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if (bits(byteMask, 2))
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bitMask = bitMask | mask(19, 16);
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if (bits(byteMask, 1))
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bitMask = bitMask | mask(15, 8);
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if (bits(byteMask, 0))
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bitMask = bitMask | mask(7, 0);
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return ((spsr & ~bitMask) | (val & bitMask));
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}
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template<class XC>
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static Addr
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readPC(XC *xc)
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{
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Addr pc = xc->readPC();
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Addr tBit = pc & (ULL(1) << PcTBitShift);
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if (tBit)
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return pc + 4;
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else
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return pc + 8;
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}
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// Perform an regular branch.
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template<class XC>
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static void
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setNextPC(XC *xc, Addr val)
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{
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xc->setNextPC((xc->readNextPC() & PcModeMask) |
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(val & ~PcModeMask));
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}
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// Perform an interworking branch.
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template<class XC>
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static void
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setIWNextPC(XC *xc, Addr val)
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{
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Addr stateBits = xc->readPC() & PcModeMask;
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Addr jBit = (ULL(1) << PcJBitShift);
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Addr tBit = (ULL(1) << PcTBitShift);
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bool thumbEE = (stateBits == (tBit | jBit));
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Addr newPc = (val & ~PcModeMask);
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if (thumbEE) {
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if (bits(newPc, 0)) {
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warn("Bad thumbEE interworking branch address %#x.\n", newPc);
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} else {
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newPc = newPc & ~mask(1);
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}
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} else {
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if (bits(newPc, 0)) {
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stateBits = tBit;
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newPc = newPc & ~mask(1);
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} else if (!bits(newPc, 1)) {
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stateBits = 0;
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} else {
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warn("Bad interworking branch address %#x.\n", newPc);
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}
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}
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newPc = newPc | stateBits;
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xc->setNextPC(newPc);
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}
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// Perform an interworking branch in ARM mode, a regular branch
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// otherwise.
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template<class XC>
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static void
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setAIWNextPC(XC *xc, Addr val)
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{
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Addr stateBits = xc->readPC() & PcModeMask;
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Addr jBit = (ULL(1) << PcJBitShift);
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Addr tBit = (ULL(1) << PcTBitShift);
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if (!jBit && !tBit) {
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setIWNextPC(xc, val);
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} else {
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setNextPC(xc, val);
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}
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}
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};
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}
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#endif //__ARCH_ARM_INSTS_STATICINST_HH__
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