b5736ba4ef
A few prior changesets have changed the gem5 output in a way that wont cause errors but may be confusing for someone trying to debug the regressions. Ones that I caught were: - no more "warn: <hash address" - typo in the ALPHA Prefetch unimplemented warning Additionaly, the last updated stats changes rearrange the ordering of the stats output even though they are still correct stats (gem5 is smart enough to detect this). All the regressions pass w/the same stats even though it looks like they are being changed.
255 lines
28 KiB
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255 lines
28 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.118740 # Number of seconds simulated
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sim_ticks 118740049000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 1530436 # Simulator instruction rate (inst/s)
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host_tick_rate 1977344021 # Simulator tick rate (ticks/s)
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host_mem_usage 196484 # Number of bytes of host memory used
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host_seconds 60.05 # Real time elapsed on the host
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sim_insts 91903056 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 19996198 # DTB read hits
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system.cpu.dtb.read_misses 10 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 19996208 # DTB read accesses
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system.cpu.dtb.write_hits 6501103 # DTB write hits
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system.cpu.dtb.write_misses 23 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 6501126 # DTB write accesses
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system.cpu.dtb.data_hits 26497301 # DTB hits
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system.cpu.dtb.data_misses 33 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 26497334 # DTB accesses
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system.cpu.itb.fetch_hits 91903090 # ITB hits
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system.cpu.itb.fetch_misses 47 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 91903137 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 389 # Number of system calls
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system.cpu.numCycles 237480098 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_insts 91903056 # Number of instructions executed
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system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
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system.cpu.num_func_calls 2059216 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 7465012 # number of instructions that are conditional controls
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system.cpu.num_int_insts 79581109 # number of integer instructions
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system.cpu.num_fp_insts 6862064 # number of float instructions
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system.cpu.num_int_register_reads 115028592 # number of times the integer registers were read
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system.cpu.num_int_register_writes 62575473 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 6071661 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 5851888 # number of times the floating registers were written
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system.cpu.num_mem_refs 26497334 # number of memory refs
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system.cpu.num_load_insts 19996208 # Number of load instructions
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system.cpu.num_store_insts 6501126 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 237480098 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.icache.replacements 6681 # number of replacements
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system.cpu.icache.tagsinuse 1418.037996 # Cycle average of tags in use
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system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
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system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
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system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
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system.cpu.icache.overall_hits 91894580 # number of overall hits
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system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
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system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
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system.cpu.icache.overall_misses 8510 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 157 # number of replacements
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system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
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system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
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system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
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system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits 26495078 # number of overall hits
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system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
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system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses 2223 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency 54507.422402 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency 54507.422402 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.writebacks 107 # number of writebacks
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.dcache.ReadReq_mshr_miss_latency 22949000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency 91552000 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 114501000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency 114501000 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041 # average WriteReq mshr miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.replacements 0 # number of replacements
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system.cpu.l2cache.tagsinuse 2074.048594 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 5951 # Total number of references to valid blocks.
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system.cpu.l2cache.sampled_refs 3109 # Sample count of references to valid blocks.
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system.cpu.l2cache.avg_refs 1.914120 # Average number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.occ_blocks::0 2056.253411 # Average occupied blocks per context
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system.cpu.l2cache.occ_blocks::1 17.795183 # Average occupied blocks per context
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system.cpu.l2cache.occ_percent::0 0.062752 # Average percentage of cache occupancy
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system.cpu.l2cache.occ_percent::1 0.000543 # Average percentage of cache occupancy
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system.cpu.l2cache.ReadReq_hits 5942 # number of ReadReq hits
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system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits
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system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits
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system.cpu.l2cache.demand_hits 5968 # number of demand (read+write) hits
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system.cpu.l2cache.overall_hits 5968 # number of overall hits
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system.cpu.l2cache.ReadReq_misses 3043 # number of ReadReq misses
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system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses
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system.cpu.l2cache.demand_misses 4765 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses 4765 # number of overall misses
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system.cpu.l2cache.ReadReq_miss_latency 158236000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency 89544000 # number of ReadExReq miss cycles
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system.cpu.l2cache.demand_miss_latency 247780000 # number of demand (read+write) miss cycles
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system.cpu.l2cache.overall_miss_latency 247780000 # number of overall miss cycles
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system.cpu.l2cache.ReadReq_accesses 8985 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.demand_accesses 10733 # number of demand (read+write) accesses
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system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
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system.cpu.l2cache.ReadReq_miss_rate 0.338676 # miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_miss_rate 0.443958 # miss rate for demand accesses
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system.cpu.l2cache.overall_miss_rate 0.443958 # miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.writebacks 0 # number of writebacks
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses
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system.cpu.l2cache.demand_mshr_misses 4765 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses 4765 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_latency 68880000 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency 190600000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency 190600000 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses
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system.cpu.l2cache.demand_mshr_miss_rate 0.443958 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate 0.443958 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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---------- End Simulation Statistics ----------
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