sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
Korey Sewell b5736ba4ef alpha:o3:simple: update simout/err files 
A few prior changesets have changed the gem5 output in a way that wont cause
errors but may be confusing for someone trying to debug the regressions. Ones that I caught
were:
- no more "warn: <hash address"
- typo in the ALPHA Prefetch unimplemented warning

Additionaly, the last updated stats changes rearrange the ordering of the stats output even though
they are still correct stats (gem5 is smart enough to detect this). All the regressions pass
w/the same stats even though it looks like they are being changed.
2011-06-20 18:57:14 -04:00

255 lines
28 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 2.663444 # Number of seconds simulated
sim_ticks 2663443716000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 1486818 # Simulator instruction rate (inst/s)
host_tick_rate 2176118189 # Simulator tick rate (ticks/s)
host_mem_usage 192584 # Number of bytes of host memory used
host_seconds 1223.94 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444595663 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449492741 # DTB read accesses
system.cpu.dtb.write_hits 160728502 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162429806 # DTB write accesses
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.itb.fetch_hits 1826378510 # ITB hits
system.cpu.itb.fetch_misses 18 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 1826378528 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 164021647 # number of instructions that are conditional controls
system.cpu.num_int_insts 1725565901 # number of integer instructions
system.cpu.num_fp_insts 805526 # number of float instructions
system.cpu.num_int_register_reads 2347934659 # number of times the integer registers were read
system.cpu.num_int_register_writes 1376202618 # number of times the integer registers were written
system.cpu.num_fp_register_reads 357 # number of times the floating registers were read
system.cpu.num_fp_register_writes 345 # number of times the floating registers were written
system.cpu.num_mem_refs 611922547 # number of memory refs
system.cpu.num_load_insts 449492741 # Number of load instructions
system.cpu.num_store_insts 162429806 # Number of store instructions
system.cpu.num_idle_cycles 0 # Number of idle cycles
system.cpu.num_busy_cycles 5326887432 # Number of busy cycles
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.tagsinuse 612.356766 # Cycle average of tags in use
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
system.cpu.icache.overall_hits 1826377708 # number of overall hits
system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
system.cpu.icache.overall_misses 802 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4079.504248 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995973 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 158839182 # number of WriteReq hits
system.cpu.dcache.demand_hits 596212431 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 596212431 # number of overall hits
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1889320 # number of WriteReq misses
system.cpu.dcache.demand_misses 9111734 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 9111734 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 177010400000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 63798266000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 240808666000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 240808666000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.011755 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.015053 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.015053 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 26428.412638 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 26428.412638 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 3058802 # number of writebacks
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 9111734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 58130306000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 213473464000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.011755 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.015053 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686269 # number of replacements
system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
system.cpu.l2cache.total_refs 7565346 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 3058802 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 1000087 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 6415439 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 6415439 # number of overall hits
system.cpu.l2cache.ReadReq_misses 1807864 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 889233 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 2697097 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 2697097 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 94008928000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 46240116000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 140249044000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 140249044000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 3058802 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.250285 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.470663 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.295977 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.295977 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 1170923 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 889233 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 2697097 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 107883880000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 107883880000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.295977 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink