ee0c261e10
RISC-V makes use of load-reserved and store-conditional instructions to enable creation of lock-free concurrent data manipulation as well as ACQUIRE and RELEASE semantics for memory ordering of LR, SC, and AMO instructions (the latter of which do not follow LR/SC semantics). This patch is a correction to patch 4, which added these instructions to the implementation of RISC-V. It modifies locked_mem.hh and the implementations of lr.w, sc.w, lr.d, and sc.d to apply the proper gem5 flags and return the proper values. An important difference between gem5's LLSC semantics and RISC-V's LR/SC ones, beyond the name, is that gem5 uses 0 to indicate failure and 1 to indicate success, while RISC-V is the opposite. Strictly speaking, RISC-V uses 0 to indicate success and nonzero to indicate failure where the value would indicate the error, but currently only 1 is reserved as a failure code by the ISA reference. This is the seventh patch in the series which originally consisted of five patches that added the RISC-V ISA to gem5. The original five patches added all of the instructions and added support for more detailed CPU models and the sixth patch corrected the implementations of Linux constants and structs. There will be an eighth patch that adds some regression tests for the instructions. [Removed some commented-out code from locked_mem.hh.] Signed-off by: Alec Roelke Signed-off by: Jason Lowe-Power <jason@lowepower.com>
132 lines
5 KiB
C++
132 lines
5 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* Copyright (c) 2007-2008 The Florida State University
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* Copyright (c) 2009 The University of Edinburgh
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* Copyright (c) 2012 ARM Limited
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* Copyright (c) 2014-2015 Sven Karlsson
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2006-2007 The Regents of The University of Michigan
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* Copyright (c) 2016 The University of Virginia
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Alec Roelke
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*/
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#ifndef __ARCH_RISCV_LOCKED_MEM_HH__
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#define __ARCH_RISCV_LOCKED_MEM_HH__
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#include <stack>
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#include "arch/registers.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "debug/LLSC.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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/*
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* ISA-specific helper functions for locked memory accesses.
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*/
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namespace RiscvISA
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{
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const int WARN_FAILURE = 10000;
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// RISC-V allows multiple locks per hart, but each SC has to unlock the most
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// recent one, so we use a stack here.
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static std::stack<Addr> locked_addrs;
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template <class XC> inline void
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handleLockedSnoop(XC *xc, PacketPtr pkt, Addr cacheBlockMask)
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{
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if (locked_addrs.empty())
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return;
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Addr snoop_addr = pkt->getAddr() & cacheBlockMask;
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DPRINTF(LLSC, "Locked snoop on address %x.\n", snoop_addr);
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if ((locked_addrs.top() & cacheBlockMask) == snoop_addr)
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locked_addrs.pop();
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}
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template <class XC> inline void
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handleLockedRead(XC *xc, Request *req)
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{
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locked_addrs.push(req->getPaddr() & ~0xF);
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DPRINTF(LLSC, "[cid:%d]: Reserved address %x.\n",
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req->contextId(), req->getPaddr() & ~0xF);
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}
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template <class XC> inline void
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handleLockedSnoopHit(XC *xc)
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{}
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template <class XC> inline bool
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handleLockedWrite(XC *xc, Request *req, Addr cacheBlockMask)
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{
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// Normally RISC-V uses zero to indicate success and nonzero to indicate
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// failure (right now only 1 is reserved), but in gem5 zero indicates
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// failure and one indicates success, so here we conform to that (it should
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// be switched in the instruction's implementation)
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DPRINTF(LLSC, "[cid:%d]: locked_addrs empty? %s.\n", req->contextId(),
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locked_addrs.empty() ? "yes" : "no");
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if (!locked_addrs.empty()) {
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DPRINTF(LLSC, "[cid:%d]: addr = %x.\n", req->contextId(),
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req->getPaddr() & ~0xF);
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DPRINTF(LLSC, "[cid:%d]: last locked addr = %x.\n", req->contextId(),
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locked_addrs.top());
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}
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if (locked_addrs.empty()
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|| locked_addrs.top() != ((req->getPaddr() & ~0xF))) {
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req->setExtraData(0);
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int stCondFailures = xc->readStCondFailures();
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xc->setStCondFailures(++stCondFailures);
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if (stCondFailures % WARN_FAILURE == 0) {
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warn("%i: context %d: %d consecutive SC failures.\n",
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curTick(), xc->contextId(), stCondFailures);
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}
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return false;
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}
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if (req->isUncacheable()) {
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req->setExtraData(2);
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}
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return true;
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}
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} // namespace RiscvISA
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#endif // __ARCH_RISCV_LOCKED_MEM_HH__
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