325 lines
8.7 KiB
C++
325 lines
8.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_OZONE_FRONT_END_HH__
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#define __CPU_OZONE_FRONT_END_HH__
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#include <deque>
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#include "arch/utility.hh"
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#include "config/the_isa.hh"
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#include "cpu/o3/bpred_unit.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/timebuf.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/eventq.hh"
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#include "sim/stats.hh"
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class ThreadContext;
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class MemObject;
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template <class>
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class OzoneThreadState;
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class PageTable;
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template <class>
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class TimeBuffer;
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template <class Impl>
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class FrontEnd
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{
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::CPUType CPUType;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::CPUType::OzoneTC OzoneTC;
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typedef typename Impl::CPUType::CommStruct CommStruct;
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/** IcachePort class. Handles doing the communication with the
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* cache/memory.
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*/
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class IcachePort : public Port
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{
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protected:
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/** Pointer to FE. */
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FrontEnd<Impl> *fe;
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public:
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/** Default constructor. */
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IcachePort(FrontEnd<Impl> *_fe)
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: fe(_fe)
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{ }
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protected:
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/** Atomic version of receive. Panics. */
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virtual Tick recvAtomic(PacketPtr pkt);
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/** Functional version of receive. Panics. */
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virtual void recvFunctional(PacketPtr pkt);
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/** Receives status change. Other than range changing, panics. */
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virtual void recvStatusChange(Status status);
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/** Returns the address ranges of this device. */
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop)
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{ resp.clear(); snoop = true; }
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/** Timing version of receive. Handles setting fetch to the
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* proper status to start fetching. */
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virtual bool recvTiming(PacketPtr pkt);
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/** Handles doing a retry of a failed fetch. */
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virtual void recvRetry();
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};
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FrontEnd(Params *params);
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std::string name() const;
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void setCPU(CPUType *cpu_ptr);
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void setBackEnd(BackEnd *back_end_ptr)
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{ backEnd = back_end_ptr; }
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void setCommBuffer(TimeBuffer<CommStruct> *_comm);
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void setTC(ThreadContext *tc_ptr);
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void setThreadState(OzoneThreadState<Impl> *thread_ptr)
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{ thread = thread_ptr; }
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void regStats();
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Port *getIcachePort() { return &icachePort; }
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void tick();
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Fault fetchCacheLine();
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void processInst(DynInstPtr &inst);
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void squash(const InstSeqNum &squash_num, const Addr &next_PC,
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const bool is_branch = false, const bool branch_taken = false);
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DynInstPtr getInst();
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void processCacheCompletion(PacketPtr pkt);
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void addFreeRegs(int num_freed);
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bool isEmpty() { return instBuffer.empty(); }
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void switchOut();
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void doSwitchOut();
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void takeOverFrom(ThreadContext *old_tc = NULL);
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bool isSwitchedOut() { return switchedOut; }
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bool switchedOut;
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private:
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void recvRetry();
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bool updateStatus();
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void checkBE();
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DynInstPtr getInstFromCacheline();
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void renameInst(DynInstPtr &inst);
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// Returns true if we need to stop the front end this cycle
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bool processBarriers(DynInstPtr &inst);
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void handleFault(Fault &fault);
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public:
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Fault getFault() { return fetchFault; }
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private:
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Fault fetchFault;
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// Align an address (typically a PC) to the start of an I-cache block.
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// We fold in the PISA 64- to 32-bit conversion here as well.
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Addr icacheBlockAlignPC(Addr addr)
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{
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return (addr & ~(cacheBlkMask));
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}
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InstSeqNum getAndIncrementInstSeq()
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{ return cpu->globalSeqNum++; }
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public:
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CPUType *cpu;
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BackEnd *backEnd;
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ThreadContext *tc;
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OzoneThreadState<Impl> *thread;
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enum Status {
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Running,
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Idle,
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IcacheWaitResponse,
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IcacheWaitRetry,
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IcacheAccessComplete,
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SerializeBlocked,
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SerializeComplete,
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RenameBlocked,
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QuiescePending,
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TrapPending,
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BEBlocked
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};
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Status status;
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private:
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TimeBuffer<CommStruct> *comm;
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typename TimeBuffer<CommStruct>::wire fromCommit;
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typedef typename Impl::BranchPred BranchPred;
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BranchPred branchPred;
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IcachePort icachePort;
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RequestPtr memReq;
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/** Mask to get a cache block's address. */
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Addr cacheBlkMask;
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unsigned cacheBlkSize;
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Addr cacheBlkPC;
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/** The cache line being fetched. */
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uint8_t *cacheData;
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bool fetchCacheLineNextCycle;
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bool cacheBlkValid;
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bool cacheBlocked;
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/** The packet that is waiting to be retried. */
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PacketPtr retryPkt;
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public:
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RenameTable<Impl> renameTable;
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private:
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Addr PC;
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Addr nextPC;
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public:
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void setPC(Addr val) { PC = val; }
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void setNextPC(Addr val) { nextPC = val; }
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void wakeFromQuiesce();
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void dumpInsts();
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private:
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TimeBuffer<int> numInstsReady;
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typedef typename std::deque<DynInstPtr> InstBuff;
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typedef typename InstBuff::iterator InstBuffIt;
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InstBuff feBuffer;
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InstBuff instBuffer;
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int instBufferSize;
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int maxInstBufferSize;
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int latency;
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int width;
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int freeRegs;
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int numPhysRegs;
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bool serializeNext;
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DynInstPtr barrierInst;
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public:
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bool interruptPending;
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private:
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// number of idle cycles
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/*
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Stats::Average notIdleFraction;
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Stats::Formula idleFraction;
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*/
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// @todo: Consider making these vectors and tracking on a per thread basis.
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/** Stat for total number of cycles stalled due to an icache miss. */
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Stats::Scalar icacheStallCycles;
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/** Stat for total number of fetched instructions. */
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Stats::Scalar fetchedInsts;
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Stats::Scalar fetchedBranches;
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/** Stat for total number of predicted branches. */
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Stats::Scalar predictedBranches;
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/** Stat for total number of cycles spent fetching. */
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Stats::Scalar fetchCycles;
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Stats::Scalar fetchIdleCycles;
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/** Stat for total number of cycles spent squashing. */
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Stats::Scalar fetchSquashCycles;
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/** Stat for total number of cycles spent blocked due to other stages in
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* the pipeline.
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*/
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Stats::Scalar fetchBlockedCycles;
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/** Stat for total number of fetched cache lines. */
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Stats::Scalar fetchedCacheLines;
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Stats::Scalar fetchIcacheSquashes;
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/** Distribution of number of instructions fetched each cycle. */
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Stats::Distribution fetchNisnDist;
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// Stats::Vector qfull_iq_occupancy;
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// Stats::VectorDistribution qfull_iq_occ_dist_;
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Stats::Formula idleRate;
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Stats::Formula branchRate;
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Stats::Formula fetchRate;
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Stats::Scalar IFQCount; // cumulative IFQ occupancy
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Stats::Formula IFQOccupancy;
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Stats::Formula IFQLatency;
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Stats::Scalar IFQFcount; // cumulative IFQ full count
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Stats::Formula IFQFullRate;
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Stats::Scalar dispatchCountStat;
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Stats::Scalar dispatchedSerializing;
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Stats::Scalar dispatchedTempSerializing;
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Stats::Scalar dispatchSerializeStallCycles;
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Stats::Formula dispatchRate;
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Stats::Formula regIntFull;
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Stats::Formula regFpFull;
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};
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#endif // __CPU_OZONE_FRONT_END_HH__
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