ed38e3432c
The drain() call currently passes around a DrainManager pointer, which is now completely pointless since there is only ever one global DrainManager in the system. It also contains vestiges from the time when SimObjects had to keep track of their child objects that needed draining. This changeset moves all of the DrainState handling to the Drainable base class and changes the drain() and drainResume() calls to reflect this. Particularly, the drain() call has been updated to take no parameters (the DrainManager argument isn't needed) and return a DrainState instead of an unsigned integer (there is no point returning anything other than 0 or 1 any more). Drainable objects should return either DrainState::Draining (equivalent to returning 1 in the old system) if they need more time to drain or DrainState::Drained (equivalent to returning 0 in the old system) if they are already in a consistent state. Returning DrainState::Running is considered an error. Drain done signalling is now done through the signalDrainDone() method in the Drainable class instead of using the DrainManager directly. The new call checks if the state of the object is DrainState::Draining before notifying the drain manager. This means that it is safe to call signalDrainDone() without first checking if the simulator has requested draining. The intention here is to reduce the code needed to implement draining in simple objects.
346 lines
11 KiB
C++
346 lines
11 KiB
C++
/*
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* Copyright (c) 2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <memory>
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#include "debug/Config.hh"
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#include "debug/Drain.hh"
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#include "debug/RubyDma.hh"
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#include "debug/RubyStats.hh"
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#include "mem/protocol/SequencerMsg.hh"
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#include "mem/ruby/system/DMASequencer.hh"
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#include "mem/ruby/system/System.hh"
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#include "sim/system.hh"
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DMASequencer::DMASequencer(const Params *p)
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: MemObject(p), m_version(p->version), m_controller(NULL),
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m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
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slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system,
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p->ruby_system->getAccessBackingStore()),
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system(p->system), retry(false)
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{
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assert(m_version != -1);
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}
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void
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DMASequencer::init()
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{
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MemObject::init();
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assert(m_controller != NULL);
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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m_mandatory_q_ptr->setSender(this);
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m_is_busy = false;
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m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
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slave_port.sendRangeChange();
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}
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BaseSlavePort &
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DMASequencer::getSlavePort(const std::string &if_name, PortID idx)
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{
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// used by the CPUs to connect the caches to the interconnect, and
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// for the x86 case also the interrupt master
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if (if_name != "slave") {
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// pass it along to our super class
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return MemObject::getSlavePort(if_name, idx);
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} else {
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return slave_port;
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}
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}
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DMASequencer::MemSlavePort::MemSlavePort(const std::string &_name,
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DMASequencer *_port, PortID id, RubySystem* _ruby_system,
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bool _access_backing_store)
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: QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
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ruby_system(_ruby_system), access_backing_store(_access_backing_store)
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{
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DPRINTF(RubyDma, "Created slave memport on ruby sequencer %s\n", _name);
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}
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bool
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DMASequencer::MemSlavePort::recvTimingReq(PacketPtr pkt)
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{
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DPRINTF(RubyDma, "Timing request for address %#x on port %d\n",
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pkt->getAddr(), id);
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DMASequencer *seq = static_cast<DMASequencer *>(&owner);
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if (pkt->memInhibitAsserted())
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panic("DMASequencer should never see an inhibited request\n");
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assert(isPhysMemAddress(pkt->getAddr()));
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assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
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RubySystem::getBlockSizeBytes());
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// Submit the ruby request
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RequestStatus requestStatus = seq->makeRequest(pkt);
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// If the request successfully issued then we should return true.
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// Otherwise, we need to tell the port to retry at a later point
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// and return false.
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if (requestStatus == RequestStatus_Issued) {
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DPRINTF(RubyDma, "Request %s 0x%x issued\n", pkt->cmdString(),
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pkt->getAddr());
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return true;
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}
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// Unless one is using the ruby tester, record the stalled M5 port for
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// later retry when the sequencer becomes free.
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if (!seq->m_usingRubyTester) {
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seq->retry = true;
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}
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DPRINTF(RubyDma, "Request for address %#x did not issued because %s\n",
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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return false;
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}
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void
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DMASequencer::ruby_hit_callback(PacketPtr pkt)
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{
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DPRINTF(RubyDma, "Hit callback for %s 0x%x\n", pkt->cmdString(),
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pkt->getAddr());
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// The packet was destined for memory and has not yet been turned
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// into a response
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assert(system->isMemAddr(pkt->getAddr()));
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assert(pkt->isRequest());
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slave_port.hitCallback(pkt);
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// If we had to stall the slave ports, wake it up because
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// the sequencer likely has free resources now.
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if (retry) {
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retry = false;
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DPRINTF(RubyDma,"Sequencer may now be free. SendRetry to port %s\n",
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slave_port.name());
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slave_port.sendRetryReq();
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}
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testDrainComplete();
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}
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void
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DMASequencer::testDrainComplete()
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{
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//If we weren't able to drain before, we might be able to now.
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if (drainState() == DrainState::Draining) {
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unsigned int drainCount = outstandingCount();
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DPRINTF(Drain, "Drain count: %u\n", drainCount);
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if (drainCount == 0) {
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DPRINTF(Drain, "DMASequencer done draining, signaling drain done\n");
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signalDrainDone();
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}
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}
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}
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DrainState
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DMASequencer::drain()
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{
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if (isDeadlockEventScheduled()) {
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descheduleDeadlockEvent();
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}
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// If the DMASequencer is not empty, then it needs to clear all outstanding
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// requests before it should call signalDrainDone()
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DPRINTF(Config, "outstanding count %d\n", outstandingCount());
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// Set status
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if (outstandingCount() > 0) {
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DPRINTF(Drain, "DMASequencer not drained\n");
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return DrainState::Draining;
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} else {
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return DrainState::Drained;
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}
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}
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void
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DMASequencer::MemSlavePort::hitCallback(PacketPtr pkt)
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{
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bool needsResponse = pkt->needsResponse();
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assert(!pkt->isLLSC());
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assert(!pkt->isFlush());
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DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse);
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// turn packet around to go back to requester if response expected
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if (access_backing_store) {
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ruby_system->getPhysMem()->access(pkt);
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} else if (needsResponse) {
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pkt->makeResponse();
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}
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if (needsResponse) {
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DPRINTF(RubyDma, "Sending packet back over port\n");
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// send next cycle
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schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
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} else {
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delete pkt;
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}
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DPRINTF(RubyDma, "Hit callback done!\n");
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}
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bool
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DMASequencer::MemSlavePort::isPhysMemAddress(Addr addr) const
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{
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DMASequencer *seq = static_cast<DMASequencer *>(&owner);
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return seq->system->isMemAddr(addr);
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}
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RequestStatus
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DMASequencer::makeRequest(PacketPtr pkt)
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{
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if (m_is_busy) {
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return RequestStatus_BufferFull;
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}
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uint64_t paddr = pkt->getAddr();
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uint8_t* data = pkt->getPtr<uint8_t>();
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int len = pkt->getSize();
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bool write = pkt->isWrite();
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assert(!m_is_busy); // only support one outstanding DMA request
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m_is_busy = true;
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active_request.start_paddr = paddr;
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active_request.write = write;
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active_request.data = data;
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active_request.len = len;
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active_request.bytes_completed = 0;
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active_request.bytes_issued = 0;
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active_request.pkt = pkt;
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std::shared_ptr<SequencerMsg> msg =
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std::make_shared<SequencerMsg>(clockEdge());
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msg->getPhysicalAddress() = Address(paddr);
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msg->getLineAddress() = line_address(msg->getPhysicalAddress());
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msg->getType() = write ? SequencerRequestType_ST : SequencerRequestType_LD;
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int offset = paddr & m_data_block_mask;
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msg->getLen() = (offset + len) <= RubySystem::getBlockSizeBytes() ?
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len : RubySystem::getBlockSizeBytes() - offset;
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if (write && (data != NULL)) {
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if (active_request.data != NULL) {
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msg->getDataBlk().setData(data, offset, msg->getLen());
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}
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}
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assert(m_mandatory_q_ptr != NULL);
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m_mandatory_q_ptr->enqueue(msg);
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active_request.bytes_issued += msg->getLen();
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return RequestStatus_Issued;
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}
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void
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DMASequencer::issueNext()
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{
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assert(m_is_busy);
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active_request.bytes_completed = active_request.bytes_issued;
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if (active_request.len == active_request.bytes_completed) {
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//
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// Must unset the busy flag before calling back the dma port because
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// the callback may cause a previously nacked request to be reissued
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//
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DPRINTF(RubyDma, "DMA request completed\n");
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m_is_busy = false;
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ruby_hit_callback(active_request.pkt);
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return;
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}
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std::shared_ptr<SequencerMsg> msg =
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std::make_shared<SequencerMsg>(clockEdge());
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msg->getPhysicalAddress() = Address(active_request.start_paddr +
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active_request.bytes_completed);
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assert((msg->getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
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msg->getLineAddress() = line_address(msg->getPhysicalAddress());
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msg->getType() = (active_request.write ? SequencerRequestType_ST :
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SequencerRequestType_LD);
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msg->getLen() =
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(active_request.len -
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active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
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active_request.len - active_request.bytes_completed :
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RubySystem::getBlockSizeBytes());
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if (active_request.write) {
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msg->getDataBlk().
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setData(&active_request.data[active_request.bytes_completed],
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0, msg->getLen());
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msg->getType() = SequencerRequestType_ST;
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} else {
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msg->getType() = SequencerRequestType_LD;
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}
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assert(m_mandatory_q_ptr != NULL);
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m_mandatory_q_ptr->enqueue(msg);
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active_request.bytes_issued += msg->getLen();
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DPRINTF(RubyDma,
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"DMA request bytes issued %d, bytes completed %d, total len %d\n",
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active_request.bytes_issued, active_request.bytes_completed,
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active_request.len);
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}
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void
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DMASequencer::dataCallback(const DataBlock & dblk)
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{
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assert(m_is_busy);
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int len = active_request.bytes_issued - active_request.bytes_completed;
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int offset = 0;
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if (active_request.bytes_completed == 0)
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offset = active_request.start_paddr & m_data_block_mask;
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assert(!active_request.write);
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if (active_request.data != NULL) {
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memcpy(&active_request.data[active_request.bytes_completed],
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dblk.getData(offset, len), len);
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}
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issueNext();
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}
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void
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DMASequencer::ackCallback()
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{
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issueNext();
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}
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void
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DMASequencer::recordRequestType(DMASequencerRequestType requestType)
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{
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DPRINTF(RubyStats, "Recorded statistic: %s\n",
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DMASequencerRequestType_to_string(requestType));
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}
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DMASequencer *
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DMASequencerParams::create()
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{
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return new DMASequencer(this);
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}
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