401 lines
13 KiB
C
401 lines
13 KiB
C
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Lisa Hsu
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*/
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/** @file
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* Ethernet device register definitions for the National
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* Semiconductor DP83820 Ethernet controller
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*/
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#ifndef __DEV_NS_GIGE_REG_H__
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#define __DEV_NS_GIGE_REG_H__
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/* Device Register Address Map */
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enum DeviceRegisterAddress {
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CR = 0x00,
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CFGR = 0x04,
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MEAR = 0x08,
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PTSCR = 0x0c,
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ISR = 0x10,
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IMR = 0x14,
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IER = 0x18,
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IHR = 0x1c,
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TXDP = 0x20,
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TXDP_HI = 0x24,
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TX_CFG = 0x28,
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GPIOR = 0x2c,
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RXDP = 0x30,
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RXDP_HI = 0x34,
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RX_CFG = 0x38,
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PQCR = 0x3c,
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WCSR = 0x40,
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PCR = 0x44,
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RFCR = 0x48,
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RFDR = 0x4c,
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BRAR = 0x50,
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BRDR = 0x54,
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SRR = 0x58,
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MIBC = 0x5c,
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MIB_START = 0x60,
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MIB_END = 0x88,
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VRCR = 0xbc,
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VTCR = 0xc0,
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VDR = 0xc4,
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CCSR = 0xcc,
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TBICR = 0xe0,
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TBISR = 0xe4,
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TANAR = 0xe8,
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TANLPAR = 0xec,
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TANER = 0xf0,
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TESR = 0xf4,
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M5REG = 0xf8,
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LAST = 0xf8,
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RESERVED = 0xfc
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};
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/* Chip Command Register */
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enum ChipCommandRegister {
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CR_TXE = 0x00000001,
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CR_TXD = 0x00000002,
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CR_RXE = 0x00000004,
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CR_RXD = 0x00000008,
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CR_TXR = 0x00000010,
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CR_RXR = 0x00000020,
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CR_SWI = 0x00000080,
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CR_RST = 0x00000100
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};
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/* configuration register */
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enum ConfigurationRegisters {
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CFGR_LNKSTS = 0x80000000,
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CFGR_SPDSTS = 0x60000000,
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CFGR_SPDSTS1 = 0x40000000,
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CFGR_SPDSTS0 = 0x20000000,
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CFGR_DUPSTS = 0x10000000,
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CFGR_TBI_EN = 0x01000000,
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CFGR_RESERVED = 0x0e000000,
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CFGR_MODE_1000 = 0x00400000,
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CFGR_AUTO_1000 = 0x00200000,
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CFGR_PINT_CTL = 0x001c0000,
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CFGR_PINT_DUPSTS = 0x00100000,
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CFGR_PINT_LNKSTS = 0x00080000,
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CFGR_PINT_SPDSTS = 0x00040000,
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CFGR_TMRTEST = 0x00020000,
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CFGR_MRM_DIS = 0x00010000,
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CFGR_MWI_DIS = 0x00008000,
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CFGR_T64ADDR = 0x00004000,
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CFGR_PCI64_DET = 0x00002000,
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CFGR_DATA64_EN = 0x00001000,
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CFGR_M64ADDR = 0x00000800,
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CFGR_PHY_RST = 0x00000400,
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CFGR_PHY_DIS = 0x00000200,
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CFGR_EXTSTS_EN = 0x00000100,
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CFGR_REQALG = 0x00000080,
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CFGR_SB = 0x00000040,
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CFGR_POW = 0x00000020,
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CFGR_EXD = 0x00000010,
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CFGR_PESEL = 0x00000008,
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CFGR_BROM_DIS = 0x00000004,
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CFGR_EXT_125 = 0x00000002,
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CFGR_BEM = 0x00000001
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};
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/* EEPROM access register */
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enum EEPROMAccessRegister {
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MEAR_EEDI = 0x00000001,
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MEAR_EEDO = 0x00000002,
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MEAR_EECLK = 0x00000004,
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MEAR_EESEL = 0x00000008,
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MEAR_MDIO = 0x00000010,
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MEAR_MDDIR = 0x00000020,
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MEAR_MDC = 0x00000040,
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};
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/* PCI test control register */
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enum PCITestControlRegister {
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PTSCR_EEBIST_FAIL = 0x00000001,
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PTSCR_EEBIST_EN = 0x00000002,
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PTSCR_EELOAD_EN = 0x00000004,
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PTSCR_RBIST_FAIL = 0x000001b8,
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PTSCR_RBIST_DONE = 0x00000200,
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PTSCR_RBIST_EN = 0x00000400,
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PTSCR_RBIST_RST = 0x00002000,
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PTSCR_RBIST_RDONLY = 0x000003f9
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};
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/* interrupt status register */
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enum InterruptStatusRegister {
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ISR_RESERVE = 0x80000000,
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ISR_TXDESC3 = 0x40000000,
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ISR_TXDESC2 = 0x20000000,
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ISR_TXDESC1 = 0x10000000,
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ISR_TXDESC0 = 0x08000000,
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ISR_RXDESC3 = 0x04000000,
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ISR_RXDESC2 = 0x02000000,
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ISR_RXDESC1 = 0x01000000,
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ISR_RXDESC0 = 0x00800000,
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ISR_TXRCMP = 0x00400000,
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ISR_RXRCMP = 0x00200000,
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ISR_DPERR = 0x00100000,
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ISR_SSERR = 0x00080000,
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ISR_RMABT = 0x00040000,
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ISR_RTAB = 0x00020000,
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ISR_RXSOVR = 0x00010000,
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ISR_HIBINT = 0x00008000,
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ISR_PHY = 0x00004000,
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ISR_PME = 0x00002000,
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ISR_SWI = 0x00001000,
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ISR_MIB = 0x00000800,
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ISR_TXURN = 0x00000400,
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ISR_TXIDLE = 0x00000200,
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ISR_TXERR = 0x00000100,
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ISR_TXDESC = 0x00000080,
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ISR_TXOK = 0x00000040,
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ISR_RXORN = 0x00000020,
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ISR_RXIDLE = 0x00000010,
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ISR_RXEARLY = 0x00000008,
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ISR_RXERR = 0x00000004,
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ISR_RXDESC = 0x00000002,
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ISR_RXOK = 0x00000001,
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ISR_ALL = 0x7FFFFFFF,
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ISR_DELAY = (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
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ISR_NODELAY = (ISR_ALL & ~ISR_DELAY),
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ISR_IMPL = (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN|
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
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ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL)
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};
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/* transmit configuration register */
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enum TransmitConfigurationRegister {
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TX_CFG_CSI = 0x80000000,
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TX_CFG_HBI = 0x40000000,
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TX_CFG_MLB = 0x20000000,
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TX_CFG_ATP = 0x10000000,
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TX_CFG_ECRETRY = 0x00800000,
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TX_CFG_BRST_DIS = 0x00080000,
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TX_CFG_MXDMA1024 = 0x00000000,
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TX_CFG_MXDMA512 = 0x00700000,
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TX_CFG_MXDMA256 = 0x00600000,
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TX_CFG_MXDMA128 = 0x00500000,
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TX_CFG_MXDMA64 = 0x00400000,
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TX_CFG_MXDMA32 = 0x00300000,
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TX_CFG_MXDMA16 = 0x00200000,
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TX_CFG_MXDMA8 = 0x00100000,
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TX_CFG_MXDMA = 0x00700000,
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TX_CFG_FLTH_MASK = 0x0000ff00,
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TX_CFG_DRTH_MASK = 0x000000ff
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};
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/*general purpose I/O control register */
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enum GeneralPurposeIOControlRegister {
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GPIOR_UNUSED = 0xffff8000,
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GPIOR_GP5_IN = 0x00004000,
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GPIOR_GP4_IN = 0x00002000,
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GPIOR_GP3_IN = 0x00001000,
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GPIOR_GP2_IN = 0x00000800,
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GPIOR_GP1_IN = 0x00000400,
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GPIOR_GP5_OE = 0x00000200,
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GPIOR_GP4_OE = 0x00000100,
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GPIOR_GP3_OE = 0x00000080,
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GPIOR_GP2_OE = 0x00000040,
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GPIOR_GP1_OE = 0x00000020,
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GPIOR_GP5_OUT = 0x00000010,
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GPIOR_GP4_OUT = 0x00000008,
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GPIOR_GP3_OUT = 0x00000004,
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GPIOR_GP2_OUT = 0x00000002,
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GPIOR_GP1_OUT = 0x00000001
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};
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/* receive configuration register */
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enum ReceiveConfigurationRegister {
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RX_CFG_AEP = 0x80000000,
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RX_CFG_ARP = 0x40000000,
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RX_CFG_STRIPCRC = 0x20000000,
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RX_CFG_RX_FD = 0x10000000,
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RX_CFG_ALP = 0x08000000,
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RX_CFG_AIRL = 0x04000000,
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RX_CFG_MXDMA512 = 0x00700000,
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RX_CFG_MXDMA = 0x00700000,
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RX_CFG_DRTH = 0x0000003e,
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RX_CFG_DRTH0 = 0x00000002
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};
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/* pause control status register */
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enum PauseControlStatusRegister {
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PCR_PSEN = (1 << 31),
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PCR_PS_MCAST = (1 << 30),
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PCR_PS_DA = (1 << 29),
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PCR_STHI_8 = (3 << 23),
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PCR_STLO_4 = (1 << 23),
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PCR_FFHI_8K = (3 << 21),
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PCR_FFLO_4K = (1 << 21),
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PCR_PAUSE_CNT = 0xFFFE
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};
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/*receive filter/match control register */
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enum ReceiveFilterMatchControlRegister {
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RFCR_RFEN = 0x80000000,
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RFCR_AAB = 0x40000000,
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RFCR_AAM = 0x20000000,
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RFCR_AAU = 0x10000000,
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RFCR_APM = 0x08000000,
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RFCR_APAT = 0x07800000,
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RFCR_APAT3 = 0x04000000,
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RFCR_APAT2 = 0x02000000,
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RFCR_APAT1 = 0x01000000,
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RFCR_APAT0 = 0x00800000,
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RFCR_AARP = 0x00400000,
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RFCR_MHEN = 0x00200000,
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RFCR_UHEN = 0x00100000,
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RFCR_ULM = 0x00080000,
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RFCR_RFADDR = 0x000003ff
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};
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/* receive filter/match data register */
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enum ReceiveFilterMatchDataRegister {
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RFDR_BMASK = 0x00030000,
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RFDR_RFDATA0 = 0x000000ff,
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RFDR_RFDATA1 = 0x0000ff00
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};
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/* management information base control register */
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enum ManagementInformationBaseControlRegister {
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MIBC_MIBS = 0x00000008,
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MIBC_ACLR = 0x00000004,
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MIBC_FRZ = 0x00000002,
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MIBC_WRN = 0x00000001
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};
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/* VLAN/IP receive control register */
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enum VLANIPReceiveControlRegister {
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VRCR_RUDPE = 0x00000080,
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VRCR_RTCPE = 0x00000040,
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VRCR_RIPE = 0x00000020,
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VRCR_IPEN = 0x00000010,
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VRCR_DUTF = 0x00000008,
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VRCR_DVTF = 0x00000004,
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VRCR_VTREN = 0x00000002,
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VRCR_VTDEN = 0x00000001
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};
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/* VLAN/IP transmit control register */
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enum VLANIPTransmitControlRegister {
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VTCR_PPCHK = 0x00000008,
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VTCR_GCHK = 0x00000004,
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VTCR_VPPTI = 0x00000002,
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VTCR_VGTI = 0x00000001
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};
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/* Clockrun Control/Status Register */
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enum ClockrunControlStatusRegister {
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CCSR_CLKRUN_EN = 0x00000001
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};
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/* TBI control register */
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enum TBIControlRegister {
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TBICR_MR_LOOPBACK = 0x00004000,
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TBICR_MR_AN_ENABLE = 0x00001000,
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TBICR_MR_RESTART_AN = 0x00000200
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};
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/* TBI status register */
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enum TBIStatusRegister {
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TBISR_MR_LINK_STATUS = 0x00000020,
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TBISR_MR_AN_COMPLETE = 0x00000004
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};
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/* TBI auto-negotiation advertisement register */
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enum TBIAutoNegotiationAdvertisementRegister {
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TANAR_NP = 0x00008000,
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TANAR_RF2 = 0x00002000,
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TANAR_RF1 = 0x00001000,
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TANAR_PS2 = 0x00000100,
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TANAR_PS1 = 0x00000080,
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TANAR_HALF_DUP = 0x00000040,
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TANAR_FULL_DUP = 0x00000020,
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TANAR_UNUSED = 0x00000E1F
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};
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/* M5 control register */
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enum M5ControlRegister {
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M5REG_RESERVED = 0xfffffffc,
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M5REG_RSS = 0x00000004,
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M5REG_RX_THREAD = 0x00000002,
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M5REG_TX_THREAD = 0x00000001
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};
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struct ns_desc32 {
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uint32_t link; /* link field to next descriptor in linked list */
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uint32_t bufptr; /* pointer to the first fragment or buffer */
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uint32_t cmdsts; /* command/status field */
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uint32_t extsts; /* extended status field for VLAN and IP info */
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};
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struct ns_desc64 {
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uint64_t link; /* link field to next descriptor in linked list */
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uint64_t bufptr; /* pointer to the first fragment or buffer */
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uint32_t cmdsts; /* command/status field */
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uint32_t extsts; /* extended status field for VLAN and IP info */
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};
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/* cmdsts flags for descriptors */
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enum CMDSTSFlatsForDescriptors {
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CMDSTS_OWN = 0x80000000,
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CMDSTS_MORE = 0x40000000,
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CMDSTS_INTR = 0x20000000,
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CMDSTS_ERR = 0x10000000,
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CMDSTS_OK = 0x08000000,
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CMDSTS_LEN_MASK = 0x0000ffff,
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CMDSTS_DEST_MASK = 0x01800000,
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CMDSTS_DEST_SELF = 0x00800000,
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CMDSTS_DEST_MULTI = 0x01000000
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};
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/* extended flags for descriptors */
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enum ExtendedFlagsForDescriptors {
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EXTSTS_UDPERR = 0x00400000,
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EXTSTS_UDPPKT = 0x00200000,
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EXTSTS_TCPERR = 0x00100000,
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EXTSTS_TCPPKT = 0x00080000,
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EXTSTS_IPERR = 0x00040000,
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EXTSTS_IPPKT = 0x00020000
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};
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/* speed status */
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static inline int
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SPDSTS_POLARITY(int lnksts)
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{
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return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
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(lnksts ? CFGR_LNKSTS : 0));
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}
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#endif /* __DEV_NS_GIGE_REG_H__ */
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