gem5/src/arch
Gabe Black 3a1428365a ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
2011-07-02 22:35:04 -07:00
..
alpha ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
arm ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
generic ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
mips ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
noisa SCons: Support building without an ISA 2010-11-19 18:00:39 -06:00
power ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
sparc ISA: Use readBytes/writeBytes for all instruction level memory operations. 2011-07-02 22:34:29 -07:00
x86 ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem. 2011-07-02 22:35:04 -07:00
isa_parser.py ISA parser: Loosen the regular expressions matching filenames. 2011-06-07 00:46:54 -07:00
micro_asm.py scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access 2009-09-22 15:24:16 -07:00
micro_asm_test.py Add a second section to make sure the ROM is extended properly. 2007-05-31 22:21:21 +00:00
SConscript scons: rename TraceFlags to DebugFlags 2011-06-02 17:36:21 -07:00