gem5/src/mem
Ron Dreslinski eafb5c4936 Still missing prefetch and tags directories as well as cache builder.
Some implementation details were left blank still, need to fill them in.

src/SConscript:
    Reorder build to compile all files first
src/mem/cache/cache.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/miss_queue.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
    More changesets pulled, now compiles everything in /miss directory and in the root directory
src/mem/packet.hh:
    Add some more support, need to clean some of it out once everything is working

--HG--
extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
2006-06-29 16:07:19 -04:00
..
cache Still missing prefetch and tags directories as well as cache builder. 2006-06-29 16:07:19 -04:00
config Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
bridge.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
bridge.hh Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
bus.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
bus.hh minor header cleanups 2006-06-17 18:40:40 -04:00
mem_object.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
mem_object.hh Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
packet.cc Backing in more changsets, getting closer to compile 2006-06-28 14:35:00 -04:00
packet.hh Still missing prefetch and tags directories as well as cache builder. 2006-06-29 16:07:19 -04:00
page_table.cc change the page table from map to hash_map and create small cache to to speed up lookups 2006-06-27 15:04:11 -04:00
page_table.hh change the page table from map to hash_map and create small cache to to speed up lookups 2006-06-27 15:04:11 -04:00
physical.cc Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
physical.hh Move SimObject creation and Port connection loops 2006-06-13 23:19:28 -04:00
port.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
port.hh add write/read functions that have endian conversions in them 2006-06-08 19:03:58 -04:00
port_impl.hh add write/read functions that have endian conversions in them 2006-06-08 19:03:58 -04:00
request.hh More Changes, working towards cache.cc compiling. Headers cleaned up. 2006-06-28 17:28:33 -04:00
translating_port.cc Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
translating_port.hh Updated Authors from bk prs info 2006-05-31 19:26:56 -04:00
vport.cc Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh. 2006-06-06 17:32:21 -04:00
vport.hh add write/read functions that have endian conversions in them 2006-06-08 19:03:58 -04:00