431 lines
14 KiB
C++
431 lines
14 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Kevin Lim
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*/
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#include <algorithm>
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#include "arch/sparc/faults.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "mem/page_table.hh"
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#include "sim/process.hh"
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#endif
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using namespace std;
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namespace SparcISA
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{
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FaultName InternalProcessorError::_name = "intprocerr";
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TrapType InternalProcessorError::_trapType = 0x029;
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FaultPriority InternalProcessorError::_priority = 4;
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FaultStat InternalProcessorError::_count;
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FaultName MemAddressNotAligned::_name = "unalign";
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TrapType MemAddressNotAligned::_trapType = 0x034;
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FaultPriority MemAddressNotAligned::_priority = 10;
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FaultStat MemAddressNotAligned::_count;
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FaultName PowerOnReset::_name = "pow_reset";
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TrapType PowerOnReset::_trapType = 0x001;
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FaultPriority PowerOnReset::_priority = 0;
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FaultStat PowerOnReset::_count;
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FaultName WatchDogReset::_name = "watch_dog_reset";
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TrapType WatchDogReset::_trapType = 0x002;
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FaultPriority WatchDogReset::_priority = 1;
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FaultStat WatchDogReset::_count;
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FaultName ExternallyInitiatedReset::_name = "extern_reset";
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TrapType ExternallyInitiatedReset::_trapType = 0x003;
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FaultPriority ExternallyInitiatedReset::_priority = 1;
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FaultStat ExternallyInitiatedReset::_count;
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FaultName SoftwareInitiatedReset::_name = "software_reset";
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TrapType SoftwareInitiatedReset::_trapType = 0x004;
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FaultPriority SoftwareInitiatedReset::_priority = 1;
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FaultStat SoftwareInitiatedReset::_count;
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FaultName REDStateException::_name = "red_counte";
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TrapType REDStateException::_trapType = 0x005;
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FaultPriority REDStateException::_priority = 1;
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FaultStat REDStateException::_count;
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FaultName InstructionAccessException::_name = "inst_access";
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TrapType InstructionAccessException::_trapType = 0x008;
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FaultPriority InstructionAccessException::_priority = 5;
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FaultStat InstructionAccessException::_count;
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FaultName InstructionAccessMMUMiss::_name = "inst_mmu";
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TrapType InstructionAccessMMUMiss::_trapType = 0x009;
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FaultPriority InstructionAccessMMUMiss::_priority = 2;
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FaultStat InstructionAccessMMUMiss::_count;
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FaultName InstructionAccessError::_name = "inst_error";
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TrapType InstructionAccessError::_trapType = 0x00A;
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FaultPriority InstructionAccessError::_priority = 3;
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FaultStat InstructionAccessError::_count;
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FaultName IllegalInstruction::_name = "illegal_inst";
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TrapType IllegalInstruction::_trapType = 0x010;
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FaultPriority IllegalInstruction::_priority = 7;
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FaultStat IllegalInstruction::_count;
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FaultName PrivilegedOpcode::_name = "priv_opcode";
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TrapType PrivilegedOpcode::_trapType = 0x011;
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FaultPriority PrivilegedOpcode::_priority = 6;
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FaultStat PrivilegedOpcode::_count;
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FaultName UnimplementedLDD::_name = "unimp_ldd";
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TrapType UnimplementedLDD::_trapType = 0x012;
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FaultPriority UnimplementedLDD::_priority = 6;
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FaultStat UnimplementedLDD::_count;
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FaultName UnimplementedSTD::_name = "unimp_std";
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TrapType UnimplementedSTD::_trapType = 0x013;
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FaultPriority UnimplementedSTD::_priority = 6;
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FaultStat UnimplementedSTD::_count;
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FaultName FpDisabled::_name = "fp_disabled";
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TrapType FpDisabled::_trapType = 0x020;
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FaultPriority FpDisabled::_priority = 8;
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FaultStat FpDisabled::_count;
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FaultName FpExceptionIEEE754::_name = "fp_754";
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TrapType FpExceptionIEEE754::_trapType = 0x021;
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FaultPriority FpExceptionIEEE754::_priority = 11;
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FaultStat FpExceptionIEEE754::_count;
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FaultName FpExceptionOther::_name = "fp_other";
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TrapType FpExceptionOther::_trapType = 0x022;
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FaultPriority FpExceptionOther::_priority = 11;
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FaultStat FpExceptionOther::_count;
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FaultName TagOverflow::_name = "tag_overflow";
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TrapType TagOverflow::_trapType = 0x023;
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FaultPriority TagOverflow::_priority = 14;
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FaultStat TagOverflow::_count;
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FaultName DivisionByZero::_name = "div_by_zero";
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TrapType DivisionByZero::_trapType = 0x028;
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FaultPriority DivisionByZero::_priority = 15;
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FaultStat DivisionByZero::_count;
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FaultName DataAccessException::_name = "data_access";
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TrapType DataAccessException::_trapType = 0x030;
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FaultPriority DataAccessException::_priority = 12;
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FaultStat DataAccessException::_count;
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FaultName DataAccessMMUMiss::_name = "data_mmu";
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TrapType DataAccessMMUMiss::_trapType = 0x031;
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FaultPriority DataAccessMMUMiss::_priority = 12;
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FaultStat DataAccessMMUMiss::_count;
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FaultName DataAccessError::_name = "data_error";
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TrapType DataAccessError::_trapType = 0x032;
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FaultPriority DataAccessError::_priority = 12;
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FaultStat DataAccessError::_count;
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FaultName DataAccessProtection::_name = "data_protection";
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TrapType DataAccessProtection::_trapType = 0x033;
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FaultPriority DataAccessProtection::_priority = 12;
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FaultStat DataAccessProtection::_count;
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FaultName LDDFMemAddressNotAligned::_name = "unalign_lddf";
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TrapType LDDFMemAddressNotAligned::_trapType = 0x035;
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FaultPriority LDDFMemAddressNotAligned::_priority = 10;
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FaultStat LDDFMemAddressNotAligned::_count;
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FaultName STDFMemAddressNotAligned::_name = "unalign_stdf";
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TrapType STDFMemAddressNotAligned::_trapType = 0x036;
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FaultPriority STDFMemAddressNotAligned::_priority = 10;
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FaultStat STDFMemAddressNotAligned::_count;
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FaultName PrivilegedAction::_name = "priv_action";
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TrapType PrivilegedAction::_trapType = 0x037;
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FaultPriority PrivilegedAction::_priority = 11;
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FaultStat PrivilegedAction::_count;
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FaultName LDQFMemAddressNotAligned::_name = "unalign_ldqf";
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TrapType LDQFMemAddressNotAligned::_trapType = 0x038;
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FaultPriority LDQFMemAddressNotAligned::_priority = 10;
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FaultStat LDQFMemAddressNotAligned::_count;
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FaultName STQFMemAddressNotAligned::_name = "unalign_stqf";
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TrapType STQFMemAddressNotAligned::_trapType = 0x039;
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FaultPriority STQFMemAddressNotAligned::_priority = 10;
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FaultStat STQFMemAddressNotAligned::_count;
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FaultName AsyncDataError::_name = "async_data";
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TrapType AsyncDataError::_trapType = 0x040;
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FaultPriority AsyncDataError::_priority = 2;
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FaultStat AsyncDataError::_count;
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FaultName CleanWindow::_name = "clean_win";
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TrapType CleanWindow::_trapType = 0x024;
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FaultPriority CleanWindow::_priority = 10;
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FaultStat CleanWindow::_count;
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//The enumerated faults
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FaultName InterruptLevelN::_name = "interrupt_n";
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TrapType InterruptLevelN::_baseTrapType = 0x041;
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FaultStat InterruptLevelN::_count;
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FaultName SpillNNormal::_name = "spill_n_normal";
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TrapType SpillNNormal::_baseTrapType = 0x080;
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FaultPriority SpillNNormal::_priority = 9;
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FaultStat SpillNNormal::_count;
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FaultName SpillNOther::_name = "spill_n_other";
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TrapType SpillNOther::_baseTrapType = 0x0A0;
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FaultPriority SpillNOther::_priority = 9;
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FaultStat SpillNOther::_count;
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FaultName FillNNormal::_name = "fill_n_normal";
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TrapType FillNNormal::_baseTrapType = 0x0C0;
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FaultPriority FillNNormal::_priority = 9;
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FaultStat FillNNormal::_count;
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FaultName FillNOther::_name = "fill_n_other";
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TrapType FillNOther::_baseTrapType = 0x0E0;
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FaultPriority FillNOther::_priority = 9;
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FaultStat FillNOther::_count;
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FaultName TrapInstruction::_name = "trap_inst_n";
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TrapType TrapInstruction::_baseTrapType = 0x100;
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FaultPriority TrapInstruction::_priority = 16;
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FaultStat TrapInstruction::_count;
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#if !FULL_SYSTEM
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FaultName PageTableFault::_name = "page_table_fault";
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TrapType PageTableFault::_trapType = 0x0000;
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FaultPriority PageTableFault::_priority = 0;
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FaultStat PageTableFault::_count;
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#endif
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/**
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* This sets everything up for a normal trap except for actually jumping to
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* the handler. It will need to be expanded to include the state machine in
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* the manual. Right now it assumes that traps will always be to the
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* privileged level.
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*/
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void doNormalFault(ThreadContext *tc, TrapType tt)
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{
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uint64_t TL = tc->readMiscReg(MISCREG_TL);
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uint64_t TSTATE = tc->readMiscReg(MISCREG_TSTATE);
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uint64_t PSTATE = tc->readMiscReg(MISCREG_PSTATE);
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uint64_t HPSTATE = tc->readMiscReg(MISCREG_HPSTATE);
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uint64_t CCR = tc->readMiscReg(MISCREG_CCR);
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uint64_t ASI = tc->readMiscReg(MISCREG_ASI);
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uint64_t CWP = tc->readMiscReg(MISCREG_CWP);
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uint64_t CANSAVE = tc->readMiscReg(MISCREG_CANSAVE);
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uint64_t GL = tc->readMiscReg(MISCREG_GL);
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uint64_t PC = tc->readPC();
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uint64_t NPC = tc->readNextPC();
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//Increment the trap level
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TL++;
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tc->setMiscReg(MISCREG_TL, TL);
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//Save off state
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//set TSTATE.gl to gl
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replaceBits(TSTATE, 42, 40, GL);
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//set TSTATE.ccr to ccr
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replaceBits(TSTATE, 39, 32, CCR);
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//set TSTATE.asi to asi
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replaceBits(TSTATE, 31, 24, ASI);
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//set TSTATE.pstate to pstate
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replaceBits(TSTATE, 20, 8, PSTATE);
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//set TSTATE.cwp to cwp
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replaceBits(TSTATE, 4, 0, CWP);
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//Write back TSTATE
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tc->setMiscReg(MISCREG_TSTATE, TSTATE);
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//set TPC to PC
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tc->setMiscReg(MISCREG_TPC, PC);
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//set TNPC to NPC
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tc->setMiscReg(MISCREG_TNPC, NPC);
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//set HTSTATE.hpstate to hpstate
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tc->setMiscReg(MISCREG_HTSTATE, HPSTATE);
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//TT = trap type;
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tc->setMiscReg(MISCREG_TT, tt);
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//Update the global register level
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if(1/*We're delivering the trap in priveleged mode*/)
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxGL));
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else
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tc->setMiscReg(MISCREG_GL, max<int>(GL+1, MaxPGL));
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//PSTATE.mm is unchanged
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//PSTATE.pef = whether or not an fpu is present
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//XXX We'll say there's one present, even though there aren't
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//implementations for a decent number of the instructions
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PSTATE |= (1 << 4);
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//PSTATE.am = 0
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PSTATE &= ~(1 << 3);
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if(1/*We're delivering the trap in priveleged mode*/)
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{
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//PSTATE.priv = 1
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PSTATE |= (1 << 2);
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//PSTATE.cle = PSTATE.tle
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replaceBits(PSTATE, 9, 9, PSTATE >> 8);
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}
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else
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{
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//PSTATE.priv = 0
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PSTATE &= ~(1 << 2);
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//PSTATE.cle = 0
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PSTATE &= ~(1 << 9);
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}
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//PSTATE.ie = 0
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PSTATE &= ~(1 << 1);
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//PSTATE.tle is unchanged
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//PSTATE.tct = 0
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//XXX Where exactly is this field?
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tc->setMiscReg(MISCREG_PSTATE, PSTATE);
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if(0/*We're delivering the trap in hyperprivileged mode*/)
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{
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//HPSTATE.red = 0
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HPSTATE &= ~(1 << 5);
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//HPSTATE.hpriv = 1
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HPSTATE |= (1 << 2);
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//HPSTATE.ibe = 0
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HPSTATE &= ~(1 << 10);
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//HPSTATE.tlz is unchanged
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tc->setMiscReg(MISCREG_HPSTATE, HPSTATE);
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}
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bool changedCWP = true;
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if(tt == 0x24)
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CWP++;
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else if(0x80 <= tt && tt <= 0xbf)
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CWP += (CANSAVE + 2);
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else if(0xc0 <= tt && tt <= 0xff)
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CWP--;
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else
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changedCWP = false;
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if(changedCWP)
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{
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CWP = (CWP + NWindows) % NWindows;
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tc->setMiscRegWithEffect(MISCREG_CWP, CWP);
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}
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}
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#if FULL_SYSTEM
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void SparcFault::invoke(ThreadContext * tc)
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{
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FaultBase::invoke(tc);
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countStat()++;
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//Use the SPARC trap state machine
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}
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#endif
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#if !FULL_SYSTEM
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void TrapInstruction::invoke(ThreadContext * tc)
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{
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// Should be handled in ISA.
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}
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void SpillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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Process *p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//Then adjust the PC and NPC
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Addr spillStart = lp->readSpillStart();
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tc->setPC(spillStart);
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tc->setNextPC(spillStart + sizeof(MachInst));
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tc->setNextNPC(spillStart + 2*sizeof(MachInst));
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}
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void FillNNormal::invoke(ThreadContext *tc)
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{
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doNormalFault(tc, trapType());
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Process * p = tc->getProcessPtr();
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//This will only work in faults from a SparcLiveProcess
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SparcLiveProcess *lp = dynamic_cast<SparcLiveProcess *>(p);
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assert(lp);
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//The adjust the PC and NPC
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Addr fillStart = lp->readFillStart();
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tc->setPC(fillStart);
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tc->setNextPC(fillStart + sizeof(MachInst));
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tc->setNextNPC(fillStart + 2*sizeof(MachInst));
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}
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void PageTableFault::invoke(ThreadContext *tc)
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{
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Process *p = tc->getProcessPtr();
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// address is higher than the stack region or in the current stack region
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if (vaddr > p->stack_base || vaddr > p->stack_min)
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FaultBase::invoke(tc);
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// We've accessed the next page
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if (vaddr > p->stack_min - PageBytes) {
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p->stack_min -= PageBytes;
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if (p->stack_base - p->stack_min > 8*1024*1024)
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fatal("Over max stack size for one thread\n");
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p->pTable->allocate(p->stack_min, PageBytes);
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warn("Increasing stack size by one page.");
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} else {
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FaultBase::invoke(tc);
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}
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}
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#endif
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} // namespace SparcISA
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