Andrew Bardsley eab00f4966 cpu: Allow setWhen on trace objects ... Allow setting of 'when' in trace records. This allows later times than the arbitrary record creation point to be used as inst. times		2014-05-09 18:58:47 -04:00
..
arch	arm: add preliminary ISA splits for ARM arch	2014-05-09 18:58:47 -04:00
base	stats: Method stats source	2014-05-09 18:58:46 -04:00
cpu	arch, arm: Preserve TLB bootUncacheability when switching CPUs	2014-05-09 18:58:47 -04:00
dev	dev: Set HDLCD default pixel clock for 1080p @ 60Hz	2014-05-09 18:58:46 -04:00
doc	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	sim: Add openat/fstatat syscalls and fix mremap	2014-01-24 15:29:30 -06:00
mem	mem: Squash prefetch requests from downstream caches	2014-05-09 18:58:46 -04:00
proto	mem: Edit proto Packet and enhance the python script	2014-03-07 15:56:23 -05:00
python	config: Avoid generating a reference to myself for Parent.any	2014-05-09 18:58:47 -04:00
sim	cpu: Allow setWhen on trace objects	2014-05-09 18:58:47 -04:00
unittest	unittest: Fix build errors	2014-01-30 12:21:58 -06:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	arch: teach ISA parser how to split code across files	2014-05-09 18:58:47 -04:00