97 lines
3.5 KiB
C++
97 lines
3.5 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/decode_unit.hh"
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using namespace TheISA;
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using namespace ThePipeline;
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using namespace std;
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DecodeUnit::DecodeUnit(std::string res_name, int res_id, int res_width,
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int res_latency, InOrderCPU *_cpu, ThePipeline::Params *params)
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: Resource(res_name, res_id, res_width, res_latency, _cpu)
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{
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for (ThreadID tid = 0; tid < MaxThreads; tid++) {
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regDepMap[tid] = &cpu->archRegDepMap[tid];
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}
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}
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void
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DecodeUnit::execute(int slot_num)
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{
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ResourceRequest* decode_req = reqMap[slot_num];
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DynInstPtr inst = reqMap[slot_num]->inst;
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Fault fault = reqMap[slot_num]->fault;
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ThreadID tid = inst->readTid();
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decode_req->fault = NoFault;
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switch (decode_req->cmd)
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{
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case DecodeInst:
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{
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bool done_sked = ThePipeline::createBackEndSchedule(inst);
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if (done_sked) {
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DPRINTF(InOrderDecode,
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"[tid:%i]: Setting Destination Register(s) for [sn:%i].\n",
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tid, inst->seqNum);
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regDepMap[tid]->insert(inst);
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decode_req->done();
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} else {
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DPRINTF(Resource,
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"[tid:%i] Static Inst not available to decode.\n", tid);
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DPRINTF(Resource,
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"Unable to create schedule for instruction [sn:%i] \n",
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inst->seqNum);
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DPRINTF(InOrderStall, "STALL: \n");
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decode_req->done(false);
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}
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}
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break;
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default:
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fatal("Unrecognized command to %s", resName);
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}
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}
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void
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DecodeUnit::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
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ThreadID tid)
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{
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DPRINTF(InOrderDecode,
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"[tid:%i]: Updating due to squash from stage %i after [sn:%i].\n",
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tid, stage_num, squash_seq_num);
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//cpu->removeInstsUntil(squash_seq_num, tid);
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}
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